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ps013012-1004 preliminary product specification ez80acclaim! ? flash microcontrollers ez80l92 mcu zilog worldwide headquarters ? 532 race street ? san jose, ca 95126 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com
ps013012-1004 preliminary this publication is subject to replacement by a later edition. t o determine whether a later edition exists, or to request copies of publications, contact: zilog w orldwide headquarters 532 race street san jose, ca 95126 t elephone: 408.558.8500 fax: 408.558.8300 www .zilog.com zilog is a registered trademark of zilog inc. in the united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. document disclaimer ? 2004 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a represent a tion of accuracy of the informa tion, devices, or technology described in this document . zilog also does not assume liability for intellectual proper ty infringement rela ted in any manner t o use of informa tion, devices, or technology described herein or other wise. except with the express written approval zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses or other rights are conveyed, implicitly or otherwis e, by this document under any intellectual property rights.
ps013012-1004 preliminary ez80l92 mcu product specification iii revision history each instance in t able 1 reflects a change to this document from its previous revision. t o see more detail, click the appropriate link in the table. t able 1. revision history of this document date revision level section description page # october 2 004 12 formatted to current publication standards . all t imer control registers clarified rst_en description s. 81 external memory read t iming correction to t6 label, clock rise to csx deassertion delay, in figure 48 . 205 external i/o read t iming correction to t6 label, clock rise to csx deassertion delay, in figure 51 . 208 real-t ime clock oscillator and source selection clarified language describing rtc drive frequency. 89
ps013012-1004 preliminary table of contents ez80l92 mcu product specification iv t able of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii i l ist of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ez80 ? cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 new and improved instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 clock peripheral power-down registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 gpio overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 gpio operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 nonmaskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chip selects and wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 memory and i/o chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 memory chip select operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 i/o chip select operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 wait input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chip selects during bus request/bus acknowledge cycles . . . . . . . . . . . . . . . . . . 52
ps013012-1004 preliminary table of contents ez80l92 mcu product specification v bus mode controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ez80 bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 z80 bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 intel bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 motorola bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 chip select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 watch-dog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 watch-dog timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 watch-dog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 watch-dog timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 programmable reload timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 programmable reload timers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 programmable reload timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 programmable reload timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 real-time clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 real-time clock alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock oscillator and source selection . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock recommended operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 uart functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 uart recommended usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 brg control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 uart registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 infrared encoder/decoder signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 loopback testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 spi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 spi flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
ps013012-1004 preliminary table of contents ez80l92 mcu product specification vi spi baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 data transfer procedure with spi configured as the master . . . . . . . . . . . . . . . . . 132 data transfer procedure with spi configured as a slave . . . . . . . . . . . . . . . . . . . 132 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 i 2 c s erial i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 i 2 c general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 transferring data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 i 2 c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 zilog debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 zdi-supported protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 zdi clock and data conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 zdi start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 zdi register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 zdi write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 zdi read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 operation of the ez80l92 during zdi break points . . . . . . . . . . . . . . . . . . . . . . . 165 bus requests during zdi debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 zdi write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 zdi read-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 zdi register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 on-chip instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 introduction to on-chip instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 oci activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 oci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 oci information requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ez80 ? c pu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 op-code map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 20 mhz primary crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 32 khz real-time clock crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . 199 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 external memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
ps013012-1004 preliminary table of contents ez80l92 mcu product specification vii external memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 external i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 external i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 wait state timing for read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 wait state timing for write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 general purpose i/o port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 external bus acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 external system clock driver (phi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 precharacterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 document information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 document number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 change log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 customer feedback form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
ps013012-1004 preliminary list of figures ez80l92 mcu product specification viii list of figures figure 1. ez80l92 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. 100-pin lqfp configuration of the ez80l92 . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 4. memory chip select example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 5. wait input sampling block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 6. wait state operation example (read operation) . . . . . . . . . . . . . . . . . . . . . . 52 figure 7. z80 bus mode read timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 8. z80 bus mode write timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 9. intel? bus mode signal and pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 10. intel? bus mode read timing example (separate address and d ata buses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 11. intel? bus mode write timing example (separate address and d ata buses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 12. intel? bus mode read timing example (multiplexed address and d ata bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 13. intel? bus mode write timing example (multiplexed address and d ata bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 14. motorola bus mode signal and pin mapping . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 15. motorola bus mode read timing example . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 16. motorola bus mode write timing example . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 17. watch-dog timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 18. programmable reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 19. prt single pass mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 20. prt continuous mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 21. prt timer output operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 22. real-time clock and 32khz oscillator block diagram . . . . . . . . . . . . . . . 88 figure 23. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 24. infrared system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 25. infrared data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
ps013012-1004 preliminary list of figures ez80l92 mcu product specification ix figure 26. infrared data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 27. spi master device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 28. spi slave device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 29. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 30. i 2 c clock and data relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 31. start and stop conditions in i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . 139 figure 32. i 2 c frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 33. i 2 c acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 34. clock synchronization in i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 35. typical zdi debug setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 36. schematic for building a target board zpak connector . . . . . . . . . . . . . 160 figure 37. zdi write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 38. zdi read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 39. zdi address write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 40. zdi single-byte data write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 41. zdi block data write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 42. zdi single-byte data read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 43. zdi block data read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 44. recommended crystal oscillator configuration (20mhz operation) . . . . . 198 figure 45. recommended crystal oscillator configuration (32khz operation) . . . . . 199 figure 46. icc vs. frequency (typical @ 3.3 v, 25oc) . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 47. icc vs. wait (typical @ 3.3 v, 25oc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 48. external memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 49. external memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 50. external write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 51. external i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 52. external i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 53. wait state timing for read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 54. wait state timing for write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 55. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
ps013012-1004 preliminary list of figures ez80l92 mcu product specification x figure 56. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 57. 100-lead plastic low-profile quad flat package (lqfp) . . . . . . . . . . . . . 215
ps013012-1004 preliminary list of tables ez80l92 mcu product specification xi list of t ables table 1. revision history of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii table 2. 100-pin lqfp pin identification of the ez80l92 device . . . . . . . . . . . . . . . . . 5 table 3. pin characteristics of the ez80l92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5. clock peripheral power-down register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6. clock peripheral power-down register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7. gpio mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8. port x data register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 9. port x data direction register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10. port x alternate registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 11. port x alternate registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12. interrupt vector sources by priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 13. vectored interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14. register values for memory chip select example in figure 4 . . . . . . . . . . . 50 table 15. z80 bus mode read states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 16. z80 bus mode write states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 17. intel? bus mode read states (separate address and data buses) . . . . . . . . 56 table 18. intel? bus mode write states (separate address and data buses) . . . . . . . . 57 table 19. intel? bus mode read states (multiplexed address and data bus) . . . . . . . 60 table 20. intel? bus mode write states (multiplexed address and data bus) . . . . . . . 60 table 21. motorola bus mode read states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 22. motorola bus mode write states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 23. chip select x lower bound register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 24. chip select x upper bound register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 25. chip select x control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 26. chip select x bus mode control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 27. watch-dog timer approximate time-out delays . . . . . . . . . . . . . . . . . . . . . 73 table 28. watch-dog timer control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ps013012-1004 preliminary list of tables ez80l92 mcu product specification xii table 29. watch-dog timer reset registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 30. prt single pass mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 31. prt continuous mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 32. prt timer out operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 33. timer control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 34. timer data registerslow byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 35. timer data registershigh byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 36. timer reload registerslow byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 37. timer reload registershigh byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 38. timer input source select registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 39. real-time clock seconds registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 40. real-time clock minutes registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 41. real-time clock hours registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 42. real-time clock day-of-the-week registe r . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 43. real-time clock day-of-the-month registe r . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 44. real-time clock month registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 45. real-time clock year registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 46. real-time clock century registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 47. real-time clock alarm seconds registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 48. real-time clock alarm minutes registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 49. real-time clock alarm hours registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 50. real-time clock alarm day-of-the-week registe r . . . . . . . . . . . . . . . . . . . 101 table 51. real-time clock alarm control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 52. real-time clock control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 53. uart baud rate generator registerslow byt e . . . . . . . . . . . . . . . . . . . . 110 table 54. uart baud rate generator registershigh byt e . . . . . . . . . . . . . . . . . . . 110 table 55. uart transmit holding register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 56. uart receive buffer register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 57. uart interrupt enable register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 58. uart interrupt identification register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ps013012-1004 preliminary list of tables ez80l92 mcu product specification xiii table 59. uart interrupt status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 60. uart fifo control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 61. uart line control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 62. uart character parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 63. uart modem control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 64. uart line status register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 65. uart modem status register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 66. uart scratch pad register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 67. gpio mode selection when using the irda encoder/decoder . . . . . . . . . . . 125 table 68. infrared encoder/decoder control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 69. spi clock phase a nd clock polarity o peration . . . . . . . . . . . . . . . . . . . . . . . 129 table 70. spi baud rate generator registerlow byt e . . . . . . . . . . . . . . . . . . . . . . . 133 table 71. spi baud rate generator registerhigh byt e . . . . . . . . . . . . . . . . . . . . . . . 133 table 72. spi control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 73. spi status registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 74. spi transmit shift registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 75. spi receive buffer registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 76. i 2 c master transmit status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 77. i 2 c 10-bit master transmit status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 78. i 2 c master transmit status codes for data bytes . . . . . . . . . . . . . . . . . . . . 145 table 79. i 2 c master receive status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 80. i 2 c master receive status codes for data bytes . . . . . . . . . . . . . . . . . . . . . 148 table 81. i 2 c register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 82. i 2 c slave address registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 83. i 2 c extended slave address registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 84. i 2 c data registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 85. i 2 c control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 86. i 2 c status register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 87. i 2 c status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 88. i 2 c clock control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
ps013012-1004 preliminary list of tables ez80l92 mcu product specification xiv table 89. i 2 c software reset registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 90. recommended zdi clock vs. system clock frequency . . . . . . . . . . . . . . . . 160 table 91. zdi write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 92. zdi read-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 93. zdi address match register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 94. zdi break c ontrol registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 95. zdi master control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 96. zdi write data register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 97. zdi read/write control register function s . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 98. zdi bus control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 99. instruction store 4:0 register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 100. zdi write memory registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 101. ez80 ? product id low byte registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 102. ez80 ? product id high byte registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 103. ez80 ? product id revision registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 104. zdi status registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 105. zdi read registerslow, high and uppe r . . . . . . . . . . . . . . . . . . . . . . . . 181 table 106. zdi bus control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 107. zdi read memory registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 108. oci pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 109. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 110. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 111. block transfer and compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 112. exchange instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 113. input/output instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 114. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 115. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 116. processor control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 117. program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 118. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
ps013012-1004 preliminary list of tables ez80l92 mcu product specification xv table 119. op code mapfirst op code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 120. op code mapsecond op code after 0cbh . . . . . . . . . . . . . . . . . . . . . . . 192 table 121. op code mapsecond op code after 0ddh . . . . . . . . . . . . . . . . . . . . . . 193 table 122. op code mapsecond op code after 0edh . . . . . . . . . . . . . . . . . . . . . . 194 table 123. op code mapsecond op code after 0fdh . . . . . . . . . . . . . . . . . . . . . . 195 table 124. op code mapfourth byte after 0ddh, 0cbh, and dd . . . . . . . . . . . . . . 196 table 125. op code mapfourth byte after 0fdh, 0cbh, and dd . . . . . . . . . . . . . . 1 97 table 126. recommended crystal oscillator specifications (20 mhz operation) . . . . 199 table 127. recommended crystal oscillator specifications (32 khz operation) . . . . 200 table 128. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 129. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 130. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 131. external read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 132. external i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 133. external i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 134. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 135. bus acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 136. phi system clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 137. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 1 architectural overview the ez80l92 microcontroller is a high-speed single-cycle instruction-fetch microcontrol - ler with a maximum clock speed of 50 mhz. the ez80l92 mcu is a member of zilog s ez80acclaim! ? family of flash microcontrollers. it can operate in z80-compatible addressing mode (64 kb) or full 24-bit addressing mode (16 mb). the rich peripheral set of the ez80l92 mcu makes it suitable for a variety of applications including industrial control, embedded communication, and point-of-sale terminals. features ? single-cycle instruction fetch, high-performance, pipelined ez80 ? cpu core 1 ? low power features including sleep mode, halt mode, and selective peripheral power-down control ? two uarts with independent baud rate generators ? spi with independent clock rate generator ? i 2 c with independent clock rate generator ? infrared data association (irda)-compliant infrared encoder/decoder ? new dma-like ez80 ? instructions for efficient block data transfer ? glueless external peripheral interface with 4 chip selects, individual wait state gen - erators, and an external wait input pinsupports intel-and motorola-style buses ? fixed-priority vectored interrupts (both internal and external) and interrupt controller ? real-time clock with on-chip 32 khz oscillator, selectable 50/60hz input, and separate v dd pin for battery backup ? six 16-bit counter/timers with prescalers and direct input/output drive ? watch-dog timer ? 24 bits of general-purpose i/o ? jtag and zdi debug interfaces ? 100-pin lqfp package ? 3.0C3.6 v supply voltage with 5 v tolerant inputs ? operating temperature range C standard: 0oc to +70oc C extended: C40oc to +105oc 1. for simplicity, the term ez80 ? cpu is referred to as cpu for the bulk of this document.
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 2 all signals with an overline are active low . for example, b/ w , for which word is active low , and b /w , for which byte is active low . power connections follow these conventional descriptions: block diagram figure 1 illustrates a block diagram of the ez80l92 microcontroller . connection circuit device power v cc v dd ground gnd v ss note:
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 3 figure 1. ez80l92 block diagram r tc_v r tc_x r tc_x i c serial interface bus controller ez80 cpu zilog debug interface (jtag/zdi) chip select and wa it state generator irda encoder/ decoder wa tch-dog ti mer (wdt) programmable reload ti mer/counters (6) 8-bit general purpose i/o port (gpio) crystal oscillator and system clock generator 2 serial peripheral interface (spi) interrupt controller universal asynchronous receiver/ t ransmitter (uart) scl sda sck ss miso mosi cts0/1 d cd0/1 dsr0/1 dtr0/1 ri0/1 r ts0/1 rxd0/1 txd0/1 ir_txd ir_rxd pb[7:0] pc[7:0] pd[7:0] x x phi t0_in t1_in t2_in t3_in t4_out t5_out wait cs0 cs1 cs2 cs3 nmi interrupt v ector [7:0] reset halt_slp busack instrd busreq iorq mreq rd wr jtag/zdi signals (5) data[7:0] addr[23:0] in out real-time clock and 32 khz oscillator dd in out
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 4 pin description figure 2 illustrates the pin layout of the ez80l92 mcu in the 100-pin lqfp package. t able 1 describes the pins and their functions. figure 2. 100-pin lqfp configuration of the ez80l92 pd7/ ri0 pd6/ dcd0 pd5/ dsr0 pd4/ dtr0 pd3/ cts0 pd2/ r ts0 pd1/rxd0/ir_rxd pd0/txd0/ir_txd v dd tdi trigout tck tms v ss r tc_v dd r tc_xout r tc_xin v ss v dd busack busreq nmi reset phi scl sda v ss pb7/mosi pb6/miso pb5/t5_out pb4/t4_out pb3/sck pb2/ ss pb1/t1_in pb0/t0_in v dd x out x in v ss pc7/ ri1 pc6/ dcd1 pc5/ dsr1 pc4/ dtr1 pc3/ cts1 pc2// rts1 pc1/rxd1 pc0/txd1 a d dr0 addr1 addr2 addr3 addr4 addr5 v dd v ss addr6 addr7 addr8 addr9 addr1 0 addr1 1 addr1 2 addr1 3 addr1 4 v dd v ss addr1 5 addr1 6 addr1 7 addr1 8 addr1 9 addr2 0 addr2 1 addr2 2 addr2 3 cs0 cs1 cs2 cs3 v dd v ss da t a0 da t a1 da t a2 da t a3 da t a4 da t a5 da t a6 da t a7 v dd v ss iorq mreq rd wr instrd wait 100-pin lqfp 1 10 80 90 100 tdo v dd halt_slp 91 92 93 94 95 96 97 98 99 81 82 83 84 85 86 87 88 89 76 77 78 79 9 8 7 6 5 4 3 2 1 1 20 19 18 17 16 15 14 13 12 21 25 24 23 22 30 40 50 41 42 43 44 45 46 47 48 49 31 32 33 34 35 36 37 38 39 26 27 28 29 51 60 59 58 57 56 55 54 53 52 61 70 69 68 67 66 65 64 63 62 71 75 74 73 72
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 5 t able 1. 100-pin lqfp pin identification of the ez80l92 device pin # symbol function signal direction description 1 addr0 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 2 addr1 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 3 addr2 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 4 addr3 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 5 addr4 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 6 addr5 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects.
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 6 7 v dd power supply power supply. 8 v ss ground ground. 9 addr6 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 10 addr7 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 11 addr8 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 12 addr9 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 13 addr10 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 7 14 addr11 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 15 addr12 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 16 addr13 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 17 addr14 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 18 v dd power supply power supply. 19 v ss ground ground. 20 addr15 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 8 21 addr16 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 22 addr17 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 23 addr18 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 24 addr19 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 25 addr20 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 26 addr21 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 9 27 addr22 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 28 addr23 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 29 cs0 chip select 0 output, active low cs0 low indicates that an access is occurring in the defined cs0 memory or i/ o address space. 30 cs1 chip select 1 output, active low cs1 low indicates that an access is occurring in the defined cs1 memory or i/ o address space. 31 cs2 chip select 2 output, active low cs2 low indicates that an access is occurring in the defined cs2 memory or i/ o address space. 32 cs3 chip select 3 output, active low cs3 low indicates that an access is occurring in the defined cs3 memory or i/ o address space. 33 v dd power supply power supply. 34 v ss ground ground. 35 data0 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu drives these lines only during wr ite cycles when the ez80l92 mcu i s the bus master. 36 data1 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu drives these lines only during write c ycles when the ez80l92 mcu i s the bus master. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 10 37 data2 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu d rives these lines only during write c ycles when the ez80l92 mcu i s the bus master. 38 data3 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu d rives these lines only during write c ycles when the ez80l92 mcu i s the bus master. 39 data4 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu d rives these lines only during write c ycles when the ez80l92 mcu i s the bus master. 40 data5 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu d rives these lines only during write c ycles when the ez80l92 mcu i s the bus master. 41 data6 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu d rives these lines only during write c ycles when the ez80l92 mcu i s the bus master. 42 data7 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80l92 mcu d rives these lines only during write c ycles when the ez80l92 mcu i s the bus master. 43 v dd power supply power supply. 44 v ss ground ground. 45 iorq input/output request bidirectional, active low iorq indicates that the cpu is accessing a location in i/o space. rd and wr indicate the type of access. the ez80l92 mcu d oes not drive this line during reset. it is an input in bus acknowledge cycles. 46 mreq memory request bidirectional, active low mreq low indicates that the cpu is accessing a location in memory. the rd , wr , and instrd signals indicate the type of access. the ez80l92 mcu d oes not drive this line during reset. it is an input in bus acknowledge cycles. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 11 47 rd read output, active low rd low indicates that the ez80l92 mcu i s reading from the current address location. this pin is tristated during bus acknowledge cycles. 48 wr write output, active low wr indicates that the cpu is writing to the current address location. this pin is tristated during bus acknowledge cycles. 49 instrd instruction read indicator output, active low instrd (with mreq and rd ) indicates the ez80l92 mcu i s fetching an instruction from memory. this pin is tristated during bus acknowledge cycles. 50 wait wait request input, active low driving the wait pin low forces the cpu to wait additional clock cycles for an external peripheral or external memory to complete its read or write operation. 51 reset reset schmitt trigger input, active low this signal is used to initialize the ez80l92 mcu. this input must be low for a minimum of 3 system clock cycles, and must be held low until the clock is stable. this input includes a schmitt trigger to allow rc rise times. 52 nmi nonmaskable interrupt schmitt trigger input, active low the nmi input is a higher priority input than the maskable interrupts. it is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. this input includes a schmitt trigger to allow rc rise times. 53 busreq bus request input, active low external devices can request the ez80l92 mcu t o release the memory interface bus for their use, by driving this pin low. 54 busack bus acknowledge output, active low the ez80l92 mcu r esponds to a low on busreq , by tristating the address, data, and control signals, and by driving the busack line low. during bus acknowledge cycles addr[23:0], iorq , and mreq are inputs. 55 halt_slp halt and sleep indicator output, active low a low on this pin indicates that the cpu has entered either halt or sleep mode because of execution of either a halt or slp instruction. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 12 56 v dd power supply power supply. 57 v ss ground ground. 58 rtc_xin real-time clock crystal input input this pin is the input to the low-power 32khz crystal oscillator for the real-time clock. 59 rtc_xout real-time clock crystal output bidirectional this pin is the output from the low-power 32khz crystal oscillator for the real-time clock. this pin is an input when the rtc is configured to operate from 50/60 hz input clock signals and the 32 khz crystal oscillator is disabled. 60 rtc_ v dd real-time clock power supply power supply for the real-time clock and associated 32khz oscillator. isolated from the power supply to the remainder of the chip. a battery can be connected to this pin to supply constant power to the real-time clock and 32khz oscillator. 61 v ss ground ground. 62 tms jtag test mode select input jtag mode select input. 63 tck jtag test clock input jtag and zdi clock input. 64 trigout jtag test trigger output output active high trigger event indicator. 65 tdi jtag test data in bidirectional jtag data input pin. functions as zdi data i/o pin when jtag is disabled. 66 tdo jtag test data out output jtag data output pin. 67 v dd power supply power supply. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 13 68 pd0 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. txd0 uart transmit data output this pin is used by the uart to transmit asynchronous serial data. this signal is multiplexed with pd0. ir_txd irda transmit data output this pin is used by the irda encoder/ decoder to transmit serial data. this signal is multiplexed with pd0. 69 pd1 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. rxd0 receive data input this pin is used by the uart to receive asynchronous serial data. this signal is multiplexed with pd1. ir_rxd irda receive data input this pin is used by the irda encoder/ decoder to receive serial data. this signal is multiplexed with pd1. 70 pd2 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. rts0 request to send output, active low modem control signal from uart. this signal is multiplexed with pd2. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 14 71 pd3 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. cts0 clear to send input, active low modem status signal to the uart. this signal is multiplexed with pd3. 72 pd4 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. dtr0 data terminal ready output, active low modem control signal to the uart. this signal is multiplexed with pd4. 73 pd5 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. dsr0 data set ready input, active low modem status signal to the uart. this signal is multiplexed with pd5. 74 pd6 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. dcd0 data carrier detect input, active low modem status signal to the uart. this signal is multiplexed with pd6. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 15 75 pd7 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. ri0 ring indicator input, active low modem status signal to the uart. this signal is multiplexed with pd7. 76 pc0 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. txd1 transmit data output this pin is used by the uart to transmit asynchronous serial data. this signal is multiplexed with pc0. 77 pc1 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. rxd1 receive data input this pin is used by the uart to receive asynchronous serial data. this signal is multiplexed with pc1. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 16 78 pc2 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. rts1 request to send output, active low modem control signal from uart. this signal is multiplexed with pc2. 79 pc3 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. cts1 clear to send input, active low modem status signal to the uart. this signal is multiplexed with pc3. 80 pc4 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. dtr1 data terminal ready output, active low modem control signal to the uart. this signal is multiplexed with pc4. 81 pc5 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. dsr1 data set ready input, active low modem status signal to the uart. this signal is multiplexed with pc5. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 17 82 pc6 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. dcd1 data carrier detect input, active low modem status signal to the uart. this signal is multiplexed with pc6. 83 pc7 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. ri1 ring indicator input, active low modem status signal to the uart. this signal is multiplexed with pc7. 84 v ss ground ground. 85 x in system clock oscillator input input this pin is the input to the onboard crystal oscillator for the primary system clock. if an external oscillator is used, its clock output should be connected to this pin. when a crystal is used, it should be connected between x in and x out . 86 x out system clock oscillator output output this pin is the output of the onboard crystal oscillator. when used, a crystal should be connected between x in and x out . 87 v dd power supply power supply. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 18 88 pb0 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t0_in timer 0 in input alternate clock source for programmable reload timers 0 and 2. this signal is multiplexed with pb0. 89 pb1 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t1_in timer 1 in input alternate clock source for programmable reload timers 1 and 3. this signal is multiplexed with pb1. 90 pb2 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. ss slave select input, active low the slave select input line is used to select a slave device in spi mode. this signal is multiplexed with pb2. 91 pb3 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. sck spi serial clock bidirectional spi serial clock. this signal is multiplexed with pb3. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 19 92 pb4 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t4_out timer 4 out output programmable reload timer 4 timer-out signal. this signal is multiplexed with pb4. 93 pb5 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t5_out timer 5 out output programmable reload timer 5 timer-out signal. this signal is multiplexed with pb5. 94 pb6 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. miso master in slave out bidirectional the miso line is configured as an input when the ez80l92 mcu i s an spi master device and as an output when ez80l92 mcu i s an spi slave device. this signal is multiplexed with pb6. t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 20 pin characteristics t able 2 describes the characteristics of each pin in the ez80l92 mcu s 100-pin lqfp package. 95 pb7 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. mosi master out slave in bidirectional the mosi line is configured as an output when the ez80l92 mcu i s an spi master device and as an input when the ez80l92 mcu i s an spi slave device. this signal is multiplexed with pb7. 96 v dd power supply power supply. 97 v ss ground ground. 98 sda i 2 c serial data bidirectional this pin carries the i 2 c data signal. 99 scl i 2 c serial clock bidirectional this pin is used to receive and transmit the i 2 c clock. 100 phi system clock output this pin is an output driven by the internal system clock. t able 2. pin characteristics of the ez80l92 pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/source 1 addr0 i/o o n/a y es no no no 2 addr1 i/o o n/a y es no no no 3 addr2 i/o o n/a y es no no no 4 addr3 i/o o n/a y es no no no 5 addr4 i/o o n/a y es no no no 6 addr5 i/o o n/a y es no no no 7 v dd t able 1. 100-pin lqfp pin identification of the ez80l92 device (continued) pin # symbol function signal direction description
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 21 8 v ss 9 addr6 i/o o n/a y es no no no 10 addr7 i/o o n/a y es no no no 11 addr8 i/o o n/a y es no no no 12 addr9 i/o o n/a y es no no no 13 addr10 i/o o n/a y es no no no 14 addr11 i/o o n/a y es no no no 15 addr12 i/o o n/a y es no no no 16 addr13 i/o o n/a y es no no no 17 addr14 i/o o n/a y es no no no 18 v dd 19 v ss 20 addr15 i/o o n/a y es no no no 21 addr16 i/o o n/a y es no no no 22 addr17 i/o o n/a y es no no no 23 addr18 i/o o n/a y es no no no 24 addr19 i/o o n/a y es no no no 25 addr20 i/o o n/a y es no no no 26 addr21 i/o o n/a y es no no no 27 addr22 i/o o n/a y es no no no 28 addr23 i/o o n/a y es no no no 29 cs0 o o low no no no no 30 cs1 o o low no no no no 31 cs2 o o low no no no no 32 cs3 o o low no no no no 33 v dd 34 v ss 35 data0 i/o i n/a y es no no no t able 2. pin characteristics of the ez80l92 (continued) pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/source
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 22 36 data1 i/o i n/a y es no no no 37 data2 i/o i n/a y es no no no 38 data3 i/o i n/a y es no no no 39 data4 i/o i n/a y es no no no 40 data5 i/o i n/a y es no no no 41 data6 i/o i n/a y es no no no 42 data7 i/o i n/a y es no no no 43 v dd 44 v ss 45 iorq i/o o low y es no no no 46 mreq i/o o low y es no no no 47 rd o o low no no no no 48 wr o o low no no no no 49 instrd o o low no no no no 50 wait i i low n/a no no n/a 51 reset i i low n/a up y es n/a 52 nmi i i low n/a no y es n/a 53 busreq i i low n/a no no n/a 54 busack o o low no no no no 55 halt_slp o o low no no no no 56 v dd 57 v ss 58 rtc_x in i i n/a n/a no no n/a 59 rtc_x out i/o u n/a n/a no no no 60 rtc_ v dd 61 v ss 62 tms i i n/a n/a up no n/a t able 2. pin characteristics of the ez80l92 (continued) pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/source
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 23 63 tck i i rising (in) falling (out) n/a up no n/a 64 trigout i/o o high y es no no no 65 tdi i/o i n/a y es up no no 66 tdo o o n/a y es no no no 67 v dd 68 pd0 i/o i n/a y es no no od & os 69 pd1 i/o i n/a y es no no od & os 70 pd2 i/o i n/a y es no no od & os 71 pd3 i/o i n/a y es no no od & os 72 pd4 i/o i n/a y es no no od & os 73 pd5 i/o i n/a y es no no od & os 74 pd6 i/o i n/a y es no no od & os 75 pd7 i/o i n/a y es no no od & os 76 pc0 i/o i n/a y es no no od & os 77 pc1 i/o i n/a y es no no od & os 78 pc2 i/o i n/a y es no no od & os 79 pc3 i/o i n/a y es no no od & os 80 pc4 i/o i n/a y es no no od & os 81 pc5 i/o i n/a y es no no od & os 82 pc6 i/o i n/a y es no no od & os 83 pc7 i/o i n/a y es no no od & os 84 v ss 85 x in i i n/a n/a no no n/a 86 x out o o n/a no no no no 87 v dd 88 pb0 i/o i n/a y es no no od & os 89 pb1 i/o i n/a y es no no od & os t able 2. pin characteristics of the ez80l92 (continued) pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/source
ps013012-1004 preliminary architectural overview ez80l92 mcu product specification 24 90 pb2 i/o i n/a y es no no od & os 91 pb3 i/o i n/a y es no no od & os 92 pb4 i/o i n/a y es no no od & os 93 pb5 i/o i n/a y es no no od & os 94 pb6 i/o i n/a y es no no od & os 95 pb7 i/o i n/a y es no no od & os 96 v dd 97 v ss 98 sda i/o i n/a y es up no od 99 scl i/o i n/a y es up no od 100 phi o o n/a y es no no no t able 2. pin characteristics of the ez80l92 (continued) pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/source
ps013012-1004 preliminary register map ez80l92 mcu product specification 25 register map all on-chip peripheral registers are accessed in the i/o address space. all i/o operations employ 16-bit addresses. the upper byte of the 24-bit address bus is undefined during all i/o operations (addr[23:16] = uu ). all i/o operations using 16-bit addresses within the range 0080h?0ffh are routed to the on-chip peripherals. external i/o chip selects are not generated if the address space programmed for the i/o chip selects overlaps the 0080h?0ffh address range. registers at unused addresses within the 0080h?0ffh range assigned to on-chip periph - erals are not implemented. read access to such addresses returns unpredictable values and w r ite access produces no ef fect. t able 3 diagrams the register map for the ez80l92 . t able 3. register map address (hex) mnemonic name reset (hex) cpu access page # programmable reload counter/t imers 0080 tmr0_ctl timer 0 control register 00 r/w 81 0081 tmr0_dr_l timer 0 data registerlow byte 00 r 82 tmr0_rr_l timer 0 reload registerlow byte 00 w 84 0082 tmr0_dr_h timer 0 data registerhigh byte 00 r 83 tmr0_rr_h timer 0 reload registerhigh byte 00 w 85 0083 tmr1_ctl timer 1 control register 00 r/w 81 0084 tmr1_dr_l timer 1 data registerlow byte 00 r 82 tmr1_rr_l timer 1 reload registerlow byte 00 w 84 0085 tmr1_dr_h timer 1 data registerhigh byte 00 r 83 tmr1_rr_h timer 1 reload registerhigh byte 00 w 85 0086 tmr2_ctl timer 2 control register 00 r/w 81 notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read-only if r tc is locked; read/w rite if r tc is unlocked. 4. after an external pin reset or a wdt reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b.
ps013012-1004 preliminary register map ez80l92 mcu product specification 26 programmable reload counter/t imers 0087 tmr2_dr_l timer 2 data registerlow byte 00 r 82 tmr2_rr_l timer 2 reload registerlow byte 00 w 84 0088 tmr2_dr_h timer 2 data registerhigh byte 00 r 83 tmr2_rr_h timer 2 reload registerhigh byte 00 w 85 0089 tmr3_ctl timer 3 control register 00 r/w 81 008a tmr3_dr_l timer 3 data registerlow byte 00 r 82 tmr3_rr_l timer 3 reload registerlow byte 00 w 84 008b tmr3_dr_h timer 3 data registerhigh byte 00 r 83 tmr3_rr_h timer 3 reload registerhigh byte 00 w 85 008c tmr4_ctl timer 4 control register 00 r/w 81 008d tmr4_dr_l timer 4 data registerlow byte 00 r 82 tmr4_rr_l timer 4 reload registerlow byte 00 w 84 008e tmr4_dr_h timer 4 data registerhigh byte 00 r 83 tmr4_rr_h timer 4 reload registerhigh byte 00 w 85 008f tmr5_ctl timer 5 control register 00 r/w 81 0090 tmr5_dr_l timer 5 data registerlow byte 00 r 82 tmr5_rr_l timer 5 reload registerlow byte 00 w 84 0091 tmr5_dr_h timer 5 data registerhigh byte 00 r 83 tmr5_rr_h timer 5 reload registerhigh byte 00 w 85 0092 tmr_iss timer input source select register 00 r/w 86 w atch-dog t imer 0093 wdt_ctl watch-dog timer control register 1 00/20 r/w 74 0094 wdt_rr watch-dog timer reset register xx w 75 t able 3. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read-only if r tc is locked; read/w rite if r tc is unlocked. 4. after an external pin reset or a wdt reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b.
ps013012-1004 preliminary register map ez80l92 mcu product specification 27 general-purpose input/output ports 009a pb_dr port b data register 2 xx r/w 43 009b pb_ddr port b data direction register ff r/w 44 009c pb_alt1 port b alternate register 1 00 r/w 44 009d pb_alt2 port b alternate register 2 00 r/w 44 009e pc_dr port c data register xx r/w 2 43 009f pc_ddr port c data direction register ff r/w 44 00a0 pc_alt1 port c alternate register 1 00 r/w 44 00a1 pc_alt2 port c alternate register 2 00 r/w 44 00a2 pd_dr port d data register xx r/w 2 43 00a3 pd_ddr port d data direction register ff r/w 44 00a4 pd_alt1 port d alternate register 1 00 r/w 44 00a5 pd_alt2 port d alternate register 2 00 r/w 44 chip select/w ait state generator 00a8 cs0_lbr chip select 0 lower bound register 00 r/w 67 00a9 cs0_ubr chip select 0 upper bound register ff r/w 68 00aa cs0_ctl chip select 0 control register e8 r/w 69 00ab cs1_lbr chip select 1 lower bound register 00 r/w 67 00ac cs1_ubr chip select 1 upper bound register 00 r/w 68 00ad cs1_ctl chip select 1 control register 00 r/w 69 00ae cs2_lbr chip select 2 lower bound register 00 r/w 67 00af cs2_ubr chip select 2 upper bound register 00 r/w 68 00b0 cs2_ctl chip select 2 control register 00 r/w 69 00b1 cs3_lbr chip select 3 lower bound register 00 r/w 67 t able 3. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read-only if r tc is locked; read/w rite if r tc is unlocked. 4. after an external pin reset or a wdt reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b.
ps013012-1004 preliminary register map ez80l92 mcu product specification 28 chip select/w ait state generator 00b2 cs3_ubr chip select 3 upper bound register 00 r/w 68 00b3 cs3_ctl chip select 3 control register 00 r/w 69 serial peripheral interface ( spi) block 00b8 spi_brg_l spi baud rate generator registerlow byte 02 r/w 133 00b9 spi_brg_h spi baud rate generator registerhigh byte 00 r/w 133 00ba spi_ctl spi control register 04 r/w 134 00bb spi_sr spi status register 00 r 135 00bc spi_tsr spi transmit shift register xx w 136 spi_rbr spi receive buffer register xx r 137 infrared encoder/decoder block 00bf ir_ctl infrared encoder/decoder control 00 r/w 125 universal asynchronous receiver/t ransmitter 0 (uart0) block 00c0 uart0_rbr uart 0 receive buffer register xx r 1 1 1 uart0_thr uart 0 transmit holding register xx w 1 1 1 uart0_brg_l uart 0 baud rate generator register low byte 02 r/w 1 10 00c1 uart0_ier uart 0 interrupt enable register 00 r/w 1 12 uart0_brg_h uart 0 baud rate generator register high byte 00 r/w 1 10 00c2 uart0_iir uart 0 interrupt identification register 01 r 1 13 uart0_fctl uart 0 fifo control register 00 w 1 14 00c3 uart0_lctl uart 0 line control register 00 r/w 1 15 t able 3. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read-only if r tc is locked; read/w rite if r tc is unlocked. 4. after an external pin reset or a wdt reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b.
ps013012-1004 preliminary register map ez80l92 mcu product specification 29 universal asynchronous receiver/t ransmitter 0 (uart0) block 00c4 uart0_mctl uart 0 modem control register 00 r/w 1 17 00c5 uart0_lsr uart 0 line status register 60 r 1 18 00c6 uart0_msr uart 0 modem status register xx r 120 00c7 uart0_spr uart 0 scratch pad register 00 r/w 121 i2 c block 00c8 i2c_sar i 2 c slave address register 00 r/w 151 00c9 i2c_xsar i 2 c extended slave address register 00 r/w 151 00ca i2c_dr i 2 c data register 00 r/w 152 00cb i2c_ctl i 2 c control register 00 r/w 154 00cc i2c_sr i 2 c status register f8 r 155 i2c_ccr i 2 c clock control register 00 w 157 00cd i2c_srr i 2 c software reset register xx w 158 universal asynchronous receiver/t ransmitter 1 (uart1) block 00d0 uart1_rbr uart 1 receive buffer register xx r 1 1 1 uart1_thr uart 1 transmit holding register xx w 1 1 1 uart1_brg_l uart 1 baud rate generator register low byte 02 r/w 1 10 00d1 uart1_ier uart 1 interrupt enable register 00 r/w 1 12 uart1_brg_h uart 1 baud rate generator register high byte 00 r/w 1 10 00d2 uart1_iir uart 1 interrupt identification register 01 r 1 13 uart1_fctl uart 1 fifo control register 00 w 1 14 00d3 uart1_lctl uart 1 line control register 00 r/w 1 15 00d4 uart1_mctl uart 1 modem control register 00 r/w 1 17 t able 3. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read-only if r tc is locked; read/w rite if r tc is unlocked. 4. after an external pin reset or a wdt reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b.
ps013012-1004 preliminary register map ez80l92 mcu product specification 30 universal asynchronous receiver/t ransmitter 1 (uart1) block 00d5 uart1_lsr uart 1 line status register 60 r/w 1 18 00d6 uart1_msr uart 1 modem status register xx r/w 120 00d7 uart1_spr uart 1 scratch pad register 00 r/w 121 low-power control 00db clk_ppd1 clock peripheral power-down register 1 00 r/w 37 00dc clk_ppd2 clock peripheral power-down register 2 00 r/w 38 real-t ime clock 00e0 rtc_sec rtc seconds register 3 xx r/w 90 00e1 rtc_min rtc minutes register xx r/w 3 91 00e2 rtc_hrs rtc hours register xx r/w 3 92 00e3 rtc_dow rtc day-of-the-week register xx r/w 3 93 00e4 rtc_dom rtc day-of-the-month register xx r/w 3 94 00e5 rtc_mon rtc month register xx r/w 3 95 00e6 rtc_yr rtc year register xx r/w 3 96 00e7 rtc_cen rtc century register xx r/w 3 97 00e8 rtc_asec rtc alarm seconds register xx r/w 98 00e9 rtc_amin rtc alarm minutes register xx r/w 99 00ea rtc_ahrs rtc alarm hours register xx r/w 100 00eb rtc_adow rtc alarm day-of-the-week register 0x r/w 101 00ec rtc_actrl rtc alarm control register 00 r/w 102 00ed rtc_ctrl rtc control register 4 x0xxxx00b/ x0xxxx10b r/w 103 t able 3. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read-only if r tc is locked; read/w rite if r tc is unlocked. 4. after an external pin reset or a wdt reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b.
ps013012-1004 preliminary register map ez80l92 mcu product specification 31 chip select bus mode control 00f0 cs0_bmc chip select 0 bus mode control register 02h r/w 70 00f1 cs1_bmc chip select 1 bus mode control register 02h r/w 70 00f2 cs2_bmc chip select 2 bus mode control register 02h r/w 70 00f3 cs3_bmc chip select 3 bus mode control register 02h r/w 70 t able 3. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read-only if r tc is locked; read/w rite if r tc is unlocked. 4. after an external pin reset or a wdt reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b.
ps013012-1004 preliminary ez80 ? cpu core ez80l92 mcu product specification 32 ez80 ? cpu core the ez80 ? cpu is the first 8-bit microprocessor to support 16 mb linear addressing. each software module or task under a real-time executive or operating system can operate in z80-compatible (64 kb) mode or full 24-bit (16 mb) address mode. the ez80 ? cpu instruction set is a superset of the instruction sets for the z80 and z180 cpus. z80 and z180 programs can be executed on an ez80 ? cpu with little or no modi - fication. features ? code-compatible with z80 and z180 products ? 24-bit linear address space ? single-cycle instruction fetch ? pipelined fetch, decode, and execute ? dual stack pointers for adl (24-bit) and z80 (16-bit) memory modes ? 24-bit cpu registers and alu (arithmetic logic unit) ? debug support ? nonmaskable interrupt ( nmi), plus support for 128 maskable vectored interrupts new and improved instructions ? four new block transfer instructions provide dma-like operations for memory to i/o and i/o to memory transfers. these new instructions are: C indrx (input from i/o, decrement the memory address, leave the i/o address unchanged, and repeat) C inirx (input from i/o, increment the memory address, leave the i/o address unchanged, and repeat) C otdrx (output to i/o, decrement the memory address, leave the i/o address unchanged, and repeat) C otirx (output to i/o, increment the memory address, leave the i/o address unchanged, and repeat) ? four other block transfer instructions are modified to improve performance relative to the ez80190 device. these modified instructions are: C ind2r (input from i/o, decrement the memory address, decrement the i/o address, and repeat)
ps013012-1004 preliminary ez80 ? cpu core ez80l92 mcu product specification 33 C ini2r (input from i/o, increment the memory address, increment the i/o address, and repeat) C otd2r (output to i/o, decrement the memory address, decrement the i/o address, and repeat) C oti2r (output to i/o, increment the memory address, increment the i/o address, and repeat) for more information about the ez80 ? cpu , its instruction set, and ez80 ? programming, please refer to the ez80 cpu user manual. for more information about the ez80190, please refer to the ez80190 product specification.
ps013012-1004 preliminary reset ez80l92 mcu product specification 34 reset reset operation the reset controller within the ez80l92 provides a consistent system reset (reset) function for all type of resets that may af fect the system. there are 4 events which can cause a reset : ? external reset pin assertion ? watch-dog timer (wdt) time-out when configured to generate a reset ? real-time clock alarm with the ez80 ? cpu in low-power sleep mode ? execution of a debug reset command during reset , an internal reset mode timer holds the system in reset for 257 sys - tem clock (sclk) cycles. the reset mode timer begins incrementing on the next rising edge of sclk following deactivation of all reset events ( reset pin, w atch-dog t imer , real-t ime clock, debugger) user must determine is 257 sclk cycles provides suf ficient time for the primary crystal oscillator to stabilize. reset , via the external reset pin, must always be executed following application of power (v dd ramp). w ithout reset following power -up, proper operation of the ez80l92 cannot be guaranteed. note:
ps013012-1004 preliminary low-power modes ez80l92 mcu product specification 35 low-power modes overview the ez80l92 provides a range of power -saving features. the highest level of power reduction is provided by sleep mode. the next level of power reduction is provided by the hal t instruction. the lowest level of power reduction is provided by the clock peripheral power -down registers. sleep mode execution of the ez80 ? cpu s slp instruction places the ez80l92 into sleep mode. in sleep mode, the operating characteristics are: ? primary crystal oscillator is disabled ? system clock is disabled ? ez80 ? cpu is idle ? program counter (pc) stops incrementing ? 32 khz crystal oscillator continues to operate and drive the real-time clock and the watch-dog timer (if wdt is configured to operate from the 32 khz oscillator) the ez80 ? cpu can be brought out of sleep mode by any of the following operations: ? reset via the external reset pin driven low ? reset via a real-time clock alarm ? reset via a watch-dog timer time-out (if running off of the 32 khz oscillator and configured to generate a reset upon time-out) ? reset via execution of a debug reset command after exiting sleep mode, the standard reset delay occurs to allow the primary crystal oscillator to stabilize. refer to the reset section 34 for more information. halt mode execution of the ez80 ? cpu s hal t instruction places the ez80l92 into hal t mode. in hal t mode, the operating characteristics are: ? primary crystal oscillator is enabled and continues to operate ? system clock is enabled and continues to operate
ps013012-1004 preliminary low-power modes ez80l92 mcu product specification 36 ? ez80 ? cpu is idle ? program counter (pc) stops incrementing the ez80 ? cpu can be brought out of hal t mode by any of the following operations: ? nonmaskable interrupt ( nmi) ? maskable interrupt ? reset via the external reset pin driven low ? watch-dog timer time-out (if configured to generate either an nmi or reset upon time-out) ? reset via execution of a debug reset command t o minimize current in hal t mode, the system clock should be disabled for all unused on-chip peripherals via the clock peripheral power -down registers. clock peripheral power-down registers t o reduce power , the clock peripheral power -down registers allow the system clock to be disabled to unused on-chip peripherals. upon reset , all peripherals are enabled. the clock to unused peripherals can be disabled by setting the appropriate bit in the clock peripheral power -down registers to 1. when powered down, the peripherals are com - pletely disabled. t o reenable, the bit in the clock peripheral power -down registers must be cleared to 0. many peripherals feature separate enable/disable control bits that must be appropriately set for operation. these peripheral specific enable/disable bits do not provide the same level of power reduction as the clock peripheral power -down registers. when powered down, the standard peripheral control registers are not accessible for read or w rite access. see t ables 4 and 5 .
ps013012-1004 preliminary low-power modes ez80l92 mcu product specification 37 t able 4. clock peripheral power-down register 1 ( clk_ppd1 = 00dbh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r r/w r/w r/w r/w note: r/w = read/write; r = read only. bit position v alue description 7 gpio_d_off 1 system clock to gpio port d is powered down. port d alternate functions do not operate correctly. 0 system clock to gpio port d is powered up. 6 gpio_c_off 1 system clock to gpio port c is powered down. port c alternate functions do not operate correctly. 0 system clock to gpio port c is powered up. 5 gpio_b_off 1 system clock to gpio port b is powered down. port b alternate functions do not operate correctly. 0 system clock to gpio port b is powered up. 4 reserved. 3 spi_off 1 system clock to spi is powered down. 0 system clock to spi is powered up. 2 i2c_off 1 system clock to i 2 c is powered down. 0 system clock to i 2 c is powered up. 1 uar t1_off 1 system clock to uart1 is powered down. 0 system clock to uart1 is powered up. 0 uar t0_off 1 system clock to uart0 and irda endec is powered down. 0 system clock to uart0 and irda endec is powered up.
ps013012-1004 preliminary low-power modes ez80l92 mcu product specification 38 t able 5. clock peripheral power-down register 2 ( clk_ppd2 = 00dch) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r r/w r/w r/w r/w r/w r/w note: r/w = read/write; r = read only. bit position v alue description 7 phi_off 1 phi clock output is disabled (output is high-impedance). 0 phi clock output is enabled. 6 0 reserved. 5 pr t5_off 1 system clock to prt5 is powered down. 0 system clock to prt5 is powered up. 4 pr t4_off 1 system clock to prt4 is powered down. 0 system clock to prt4 is powered up. 3 pr t3_off 1 system clock to prt3 is powered down. 0 system clock to prt3 is powered up. 2 pr t2_off 1 system clock to prt2 is powered down. 0 system clock to prt2 is powered up. 1 pr t1_off 1 system clock to prt1 is powered down. 0 system clock to prt1 is powered up. 0 pr t0_off 1 system clock to prt0 is powered down. 0 system clock to prt0 is powered up.
ps013012-1004 preliminary general-purpose input/output ez80l92 mcu product specification 39 general-purpose input/output gpio overview the ez80l92 features 24 general-purpose input/output (gpio) pins. the gpio pins are assembled as three 8-bit ports port b, port c, and port d. all port signals can be config - ured for use as either inputs or outputs. in addition, all of the port pins can be used as vec - tored interrupt sources for the ez80 ? cpu . gpio operation the gpio operation is the same for all 3 gpio ports (ports b, c, and d). each port fea - tures eight gpio port pins. the operating mode for each pin is controlled by four bits that are divided between four 8-bit registers. these gpio mode control registers are: ? port x data register (px_dr) ? port x data direction register (px_ddr) ? port x alternate register 1 (px_alt1) ? port x alternate register 2 (px_alt2) where x can be b , c , or d representing any of the three gpio ports b, c, or d. the mode for each pin is controlled by setting each register bit pertinent to the pin to be configured. for example, the operating mode for port b pin 7 ( pb7), is set by the values contained in pb_dr[7], pb_ddr[7], pb_al t1[7], and pb_al t2[7]. the combination of the gpio control register bits allows individual configuration of each port pin for nine modes. in all modes, reading of the port x data register returns the sam - pled state, or level, of the signal on the corresponding pin. t able 6 indicates the function of each port signal based upon these four register bits. after a reset event, all gpio port pins are configured as standard digital inputs, with interrupts disabled.
ps013012-1004 preliminary general-purpose input/output ez80l92 mcu product specification 40 gpio mode 1 . the port pin is configured as a standard digital output pin. the value writ - ten to the port x data register (p x _dr) is presented on the pin. gpio mode 2 . the port pin is configured as a standard digital input pin. the output is tristated (high impedance). the value stored in the port x data register produces no ef fect. as in all modes, a read from the port x data register returns the pin s value. gpio mode 2 is the default operating mode following a reset . gpio mode 3 . the port pin is configured as open-drain i/o. the gpio pins do not feature an internal pull-up to the supply voltage. t o employ the gpio pin in open-drain mode, an external pull-up resistor must connect the pin to the supply voltage. w riting a 0 to the port x data register outputs a low at the pin. w riting a 1 to the port x data register results in high-impedance output. gpio mode 4 . the port pin is configured as open-source i/o. the gpio pins do not fea - ture an internal pull-down to the supply ground. t o employ the gpio pin in open- source mode, an external pull-down resistor must connect the pin to the supply ground. t able 6. gpio mode selection gpio mode px_al t2 bits7:0 px_al t1 bits7:0 px_ddr bits7:0 px_dr bits7:0 port mode output 1 0 0 0 0 output 0 0 0 0 1 output 1 2 0 0 1 0 input from pin high impedance 0 0 1 1 input from pin high impedance 3 0 1 0 0 open-drain output 0 0 1 0 1 open-drain i/o high impedance 4 0 1 1 0 open source i/o high impedance 0 1 1 1 open source output 1 5 1 0 0 0 reserved high impedance 6 1 0 0 1 interruptdual edge triggered high impedance 7 1 0 1 0 port b, c, or dalternate function controls port i/o. 1 0 1 1 port b, c, or dalternate function controls port i/o. 8 1 1 0 0 interruptactive low high impedance 1 1 0 1 interruptactive high high impedance 9 1 1 1 0 interruptfalling edge triggered high impedance 1 1 1 1 interruptrising edge triggered high impedance
ps013012-1004 preliminary general-purpose input/output ez80l92 mcu product specification 41 w riting a 1 to the port x data register outputs a high at the pin. w riting a 0 to the port x data register results in a high-impedance output. gpio mode 5 . reserved. this pin produces high-impedance output. gpio mode 6 . this bit enables a dual edge-triggered interrupt mode. both a rising and a falling edge on the pin cause an interrupt request to be sent to the ez80 ? cpu . w riting a 1 to the port x data register bit position resets the corresponding interrupt request. w riting a 0 produces no ef fect. the programmer must set the port x data register before entering the edge-triggered interrupt mode. gpio m ode 7 . for ports b, c, and d, the port pin is configured to pass control over to the alternate (secondary) functions assigned to the pin. for example, the alternate mode func - tion for pc7 is ri1 and the alternate mode function for pb4 is the t imer 4 out. when gpio mode 7 is enabled, the pin output data and pin tristated control come from the alter - nate function's data output and tristate control, respectively . the value in the port x data register produces no ef fect on operation. input signals are sampled by the system clock before being passed to the alternate function input. gpio m ode 8 . the port pin is configured for level-sensitive interrupt modes. an interrupt request is generated when the level at the pin is the same as the level stored in the port x data register . the port pin value is sampled by the system clock. the input pin must be held at the selected interrupt level for a minimum of 2 clock periods to initiate an inter - rupt. the interrupt request remains active as long as this condition is maintained at the external source. gpio m ode 9 . the port pin is configured for single edge-triggered interrupt mode. the value in the port x data register determines if a positive or negative edge causes an inter - rupt request. a 0 in the port x data register bit sets the selected pin to generate an interrupt request for falling edges. a 1 in the port x data register bit sets the selected pin to generate an interrupt request for rising edges. the interrupt request remains active until a 1 is writ - ten to the corresponding interrupt request of the port x data register bit. w riting a 0 pro - duces no ef fect on operation. the programmer must set the port x data register before entering the edge-triggered interrupt mode. a simplified block diagram of a gpio port pin is illustrated in figure 3 . note:
ps013012-1004 preliminary general-purpose input/output ez80l92 mcu product specification 42 gpio interrupts each port pin can be used as an interrupt source. interrupts can be either level- or edge- triggered. level-t riggered interrupts when the port is configured for level-triggered interrupts, the corresponding port pin is tristated. an interrupt request is generated when the level at the pin is the same as the level stored in the port x data register . the port pin value is sampled by the system clock. the input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock cycles to initiate an interrupt. the interrupt request remains active as long as this condition is maintained at the external source. for example, if pd3 is programmed for low-level interrupt and the pin is forced low for 2 consecutive clock cycles, an interrupt request signal is generated from that port pin and sent to the ez80 ? cpu . the interrupt request signal remains active until the external device driving pd3 forces the pin high. edge-t riggered interrupts when the port is configured for edge-triggered interrupts, the corresponding port pin is tristated. if the pin receives the correct edge from an external device, the port pin gener - ates an interrupt request signal to the ez80 ? cpu . any time a port pin is configured for figure 3. gpio port pin block diagram port pin gpio register data (input) gpio register data (output) system clock system clock data bus mode 1 gnd v dd mode 1 mode 3 mode 4 dq d qd q
ps013012-1004 preliminary general-purpose input/output ez80l92 mcu product specification 43 edge-triggered interrupt, writing a 1 to that pin s port x data register causes a reset of the edge-detected interrupt. the programmer must set the bit in the port x data register to 1 before entering either single or dual edge-triggered interrupt mode for that port pin. when configured for dual edge-triggered interrupt mode (gpio mode 6), both a rising and a falling edge on the pin cause an interrupt request to be sent to the ez80 ? cpu . when configured for single edge-triggered interrupt mode (gpio mode 9), the value in the port x data register determines if a positive or negative edge causes an interrupt request. a 0 in the port x data register bit sets the selected pin to generate an interrupt request for falling edges. a 1 in the port x data register bit sets the selected pin to generate an interrupt request for rising edges. gpio control registers the 12 gpio control registers operate in groups of four with a set for each port (b, c, and d). each gpio port features a port data register , port data direction register , port alternate register 1, and port alternate register 2. port x data registers when the port pins are configured for one of the output modes, the data written to the port x data registers, detailed in t able 7 , are driven on the corresponding pins. in all modes, reading from the port x data registers always returns the current sampled value of the cor - responding pins. when the port pins are configured as edge-triggered interrupt sources, writing a 1 to the corresponding bit in the port x data register clears the interrupt signal that is sent to the ez80 ? cpu . when the port pins are configured for edge-selectable inter - rupts or level-sensitive interrupts, the value written to the port x data register bit selects the interrupt edge or interrupt level. see t able 6 for more information. t able 7. port x data register s ( pb_dr = 009ah, pc_dr = 009eh, pd_dr = 00a2h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = undefined; r/w = read/write.
ps013012-1004 preliminary general-purpose input/output ez80l92 mcu product specification 44 port x data direction registers in conjunction with the other gpio control registers, the port x data direction registers, detailed in t able 8 , control the operating modes of the gpio port pins. see t able 6 for more information. port x alternate register 1 in conjunction with the other gpio control registers, the port x alternate register 1, detailed in t able 9 , control the operating modes of the gpio port pins. see t able 6 for more information. port x alternate register 2 in conjunction with the other gpio control registers, the port x alternate register 2, detailed in t able 10 , control the operating modes of the gpio port pins. see t able 6 for more information. t able 8. port x data direction register s ( pb_ddr = 009bh, pc_ddr = 009fh, pd_ddr = 00a3h) bit 7 6 5 4 3 2 1 0 reset 1 1 1 1 1 1 1 1 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. t able 9. port x alternate registers 1 ( pb_al t1 = 009ch, pc_al t1 = 00a0h, pd_al t1 = 00a4h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. t able 10. port x alternate registers 2 ( pb_al t2 = 009dh, pc_al t2 = 00a1h, pd_al t2 = 00a5h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write.
ps013012-1004 preliminary interrupt controller ez80l92 mcu product specification 45 interrupt controller the interrupt controller on the ez80l92 routes the interrupt request signals from the inter - nal peripherals and external devices (via the gpio pins) to the ez80 ? cpu . maskable interrupts on the ez80l92 , all maskable interrupts use the ez80 ? cpu s vectored interrupt function. t able 1 1 lists the low-byte vector for each of the maskable interrupt sources. the maskable interrupt sources are listed in order of their priority , with vector 00h being the highest-priority interrupt. the full 16-bit interrupt vector is located at starting address {i[7:0], ivect[7:0]} where i[7:0] is the ez80 ? cpu s interrupt page address register . the user s program should store the interrupt service routine starting address in the two- byte interrupt vector locations. for example, for adl mode the two-byte address for the spi interrupt service routine would be stored at {00h, i[7:0], 1eh} and {00h, i[7:0], 1fh}. in z80 mode, the two-byte address for the spi interrupt service routine would be stored at t able 1 1. interrupt v ector sources by priority v ector source v ector source v ector source v ector source 00h unused 1ah uar t 1 34h port b 2 4eh port c 7 02h unused 1ch i 2 c 36h port b 3 50h port d 0 04h unused 1eh spi 38h port b 4 52h port d 1 06h unused 20h unused 3ah port b 5 54h port d 2 08h unused 22h unused 3ch port b 6 56h port d 3 0ah pr t 0 24h unused 3eh port b 7 58h port d 4 0ch pr t 1 26h unused 40h port c 0 5ah port d 5 0eh pr t 2 28h unused 42h port c 1 5ch port d 6 10h pr t 3 2ah unused 44h port c 2 5eh port d 7 12h pr t 4 2ch unused 46h port c 3 60h unused 14h pr t 5 2eh unused 48h port c 4 62h unused 16h r tc 30h port b 0 4ah port c 5 64h unused 18h uar t 0 32h port b 1 4ch port c 6 66h unused note: absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, and 66h are reserved for hardware reset, nmi, and the rst instruction.
ps013012-1004 preliminary interrupt controller ez80l92 mcu product specification 46 {mbase[7:0], i[7:0], 1eh} and {mbase, i[7:0], 1fh}. the least significant byte is stored at the lower address. when any one or more of the interrupt requests (irqs) become active, an interrupt request is generated by the interrupt controller and sent to the cpu. the corresponding 8-bit inter - rupt vector for the highest priority interrupt is placed on the 8-bit interrupt vector bus, ivect[7:0]. the interrupt vector bus is internal to the ez80l92 and is therefore not visi - ble externally . the response time of the ez80 ? cpu to an interrupt request is a function of the current instruction being executed as well as the number of w ait states being asserted. the interrupt vector , {i[7:0], ivect[7:0]}, is visible on the address bus, addr[15:0], when the interrupt service routine begins. the response of the ez80 ? cpu to a vectored interrupt on the ez80l92 is explained in t able 12 . interrupt sources are required to be active until the interrupt service routine (isr) starts. it is recommended that the interrupt page address register (i) value be changed by the user from its default value of 00h as this address can create conflicts between the nonmaskable interrupt vector , the rst instruction addresses, and the maskable interrupt vectors. t able 12. v ectored interrupt operation memory mode adl bit madl bit operation z80 mode 0 0 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect [7:0], by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is ef fectively {mbase, pc[15:0]}. ? push the 2-byte return address pc[15:0] onto the ({mbase,sps}) stack. ? the adl mode bit remains cleared to 0. ? the interrupt vector address is located at { mbase, i[7:0], ivect[7:0] }. ? pc[15:0] ( { mbase, i[7:0], ivect[7:0] } ) . ? the ending program counter is ef fectively {mbase, pc[15:0]} ? the interrupt service routine must end with reti. adl mode 1 0 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect [7:0], by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is pc[23:0]. ? push the 3-byte return address, pc[23:0], onto the spl stack. ? the adl mode bit remains set to 1. ? the interrupt vector address is located at { 00h, i[7:0], ivect[7:0] }. ? pc[15:0] ( { 00h, i[7:0], ivect[7:0] } ) . ? the ending program counter is { 00h, pc[15:0] }. ? the interrupt service routine must end with reti.
ps013012-1004 preliminary interrupt controller ez80l92 mcu product specification 47 nonmaskable interrupts an active low input on the nmi pin generates an interrupt request to the ez80 ? cpu . this nonmaskable interrupt is always serviced by the ez80 ? cpu , regardless of the state of the interrupt enable flags (ief1 and ief2). the nonmaskable interrupt is prioritized higher than all maskable interrupts. the response of the ez80 ? cpu to a nonmaskable interrupt is described in detail in the ez80 ? cpu user manual (um0077). z80 mode 0 1 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect[7:0], bus by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is ef fectively {mbase, pc[15:0]}. ? push the 2-byte return address, pc[15:0], onto the spl stack. ? push a 00h byte onto the spl stack to indicate an interrupt from z80 mode (because adl = 0). ? set the adl mode bit to 1. ? the interrupt vector address is located at { 00h, i[7:0], ivect[7:0] }. ? pc[15:0] ( { 00h, i[7:0], ivect[7:0] } ) . ? the ending program counter is { 00h, pc[15:0] }. ? the interrupt service routine must end with reti.l adl mode 1 1 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect [7:0], by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is pc[23:0]. ? push the 3-byte return address, pc[23:0], onto the spl stack. ? push a 01h byte onto the spl stack to indicate a restart from adl mode (because adl = 1). ? the adl mode bit remains set to 1. ? the interrupt vector address is located at {00h, i[7:0], ivect[7:0]}. ? pc[15:0] ( { 00h, i[7:0], ivect[7:0] } ) . ? the ending program counter is { 00h, pc[15:0] }. ? the interrupt service routine must end with reti.l t able 12. v ectored interrupt operation (continued) memory mode adl bit madl bit operation
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 48 chip selects and w ait states the ez80l92 generates four chip selects for external devices. each chip select may be programmed to access either memory space or i/o space. the memory chip selects can be individually programmed on a 64 kb boundary . the i/o chip selects can each choose a 256-byte section of i/o space. in addition, each chip select may be programmed for up to 7 wait states. memory and i/o chip selects each of the chip selects can be enabled for either the memory address space or the i/o address space, but not both. t o select the memory address space for a particular chip select, cs x _io ( cs x _ctl[4]) must be reset to 0. t o select the i/o address space for a particular chip select, cs x _io must be set to 1. after reset , the default is for all chip selects to be configured for the memory address space. for either the memory address space or the i/o address space, the individual chip selects must be enabled by setting csx_en ( cs x _ctl[3]) to 1. memory chip select operation operation of each of the memory chip selects is controlled by three control registers. t o enable a particular memory chip select, the following conditions must be met: ? the chip select is enabled by setting cs x _en to 1 ? the chip select is configured for memory by clearing cs x _io to 0 ? the address is in the associated chip select range: cs x _lbr[7:0] addr[23:16] cs x _ubr[7:0] ? no higher priority (lower number) chip select meets the above conditions ? a memory access instruction must be executing if all of the foregoing conditions are met to generate a memory chip select, then the fol - lowing actions occur: ? the appropriate chip select cs0 , cs1 , cs2 , or cs3 is asserted (driven low) ? mreq is asserted (driven low) ? depending upon the instruction, either rd or wr is asserted (driven low) if the upper and lower bounds are set to the same value ( cs x _ubr = cs x _lbr), then a particular chip select is valid for a single 64 kb page.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 49 memory chip select priority a lower -numbered chip select is granted priority over a higher -numbered chip select. for example, if the address space of chip select 0 overlaps the chip select 1 address space, chip select 0 is active. reset states on reset , chip select 0 is active for all addresses, because its lower bound register resets to 00h and its upper bound register resets to ffh . all of the other chip select lower and upper bound registers reset to 00h . memory chip select example the use of memory chip selects is demonstrated in figure 4 . the associated control reg - ister values indicated in t able 13 . in this example, all 4 chip selects are enabled and con - figured for memory addresses. also, cs1 overlaps with cs0. because cs0 is prioritized higher than cs1, cs1 is not active for much of its defined address space. figure 4. memory chip select example memory location ffffffh d00000h cfffffh a00000h 9fffffh 7fffffh 800000h 000000h cs3_ubr = ffh cs3_lbr = d0h cs2_ubr = cfh cs2_lbr = a0h cs1_ubr = 9fh cs0_ubr = 7fh cs0_lbr = cs1_lbr = 00h cs3 active 3 mb address space cs2 active 3 mb address space cs1 active 2 mb address space cs0 active 8 mb address space
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 50 i/o chip select operation i/o chip selects can only be active when the cpu is performing i/o instructions. because the i/o space is separate from the memory space in the ez80l92 device, there can never be a conflict between i/o and memory addresses. the ez80l92 supports a 16-bit i/o address. the i/o chip select logic decodes the high byte of the i/o address, addr[15:8]. because the upper byte of the address bus, addr[23:16], is ignored, the i/o devices can always be accessed from within any mem - ory mode (adl or z80). the mbase of fset value used for setting the z80 memor y mode page is also always ignored. four i/o chip selects are available with the ez80l92 . t o generate a particular i/o chip select, the following conditions must be met: ? the chip select is enabled by setting csx_en to 1 ? the chip select is configured for i/o by setting cs x _io to 1 ? an i/o chip select address match occursaddr[15:8] = cs x _lbr[7:0] ? no higher-priority (lower-number) chip select meets the above conditions ? the i/o address is not within the on-chip peripheral address range 0080h?0ffh . on- chip peripheral registers assume priority for all addresses where: 0080h addr[15:0] 00ffh ? an i/o instruction must be executing t able 13. register v alues for memory chip select example in figure 4 chip select cs x _ctl[3] cs x _en cs x _ctl[4] cs x _io cs x _lbr cs x _ubr description cs0 1 0 00h 7fh cs0 is enabled as a memory chip select. valid addresses range from 000000hC 7fffffh. cs1 1 0 00h 9fh cs1 is enabled as a memory chip select. valid addresses range from 800000hC 9fffffh. cs2 1 0 a0h cfh cs2 is enabled as a memory chip select. valid addresses range from a00000hC cfffffh. cs3 1 0 d0h ffh cs3 is enabled as a memory chip select. valid addresses range from d00000hC ffffffh.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 51 if all of the foregoing conditions are met to generate an i/o chip select, then the follow - ing actions occur: ? the appropriate chip select cs0 , cs1 , cs2 , or cs3 is asserted (driven low) ? iorq is asserted (driven low) ? depending upon the instruction, either rd or wr is asserted (driven low) wait states for each of the chip selects, programmable w ait states can be asserted to provide exter - nal devices with additional clock cycles to complete their read or w rite operations. the number of w ait states for a particular chip select is controlled by the 3-bit field cs x _wait ( cs x _ctl[7:5]). the w ait states can be independently programmed to pro - vide 0 to 7 w ait states for each chip select. the w ait states idle the cpu for the speci - fied number of system clock cycles. wait input signal similar to the programmable w ait states, an external peripheral can drive the w ait input pin to force the cpu to provide additional clock cycles to complete its read or w rite operation. driving the w ait pin low stalls the cpu. the cpu resumes operation on the first rising edge of the internal system clock following deassertion of the w ait pin. if the w ait pin is to be driven by an external device, the corresponding chip select for the device must be programmed to provide at least one w ait state. due to input sampling of the w ait input pin (shown in figure 5 ), one pro - grammable w ait state is required to allow the external peripheral suf ficient time to assert the w ait pin. it is recommended that the corresponding chip select for the external device be programmed to provide the maximum num - ber of w ait states (seven). figure 5. w ait input sampling block diagram caution: system clock dq w ait pin ez80 cpu
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 52 an example of w ait state operation is illustrated in figure 6 . in this example, the chip select is configured to provide a single w ait state. the external peripheral being accessed drives the w ait pin low to request assertion of an additional w ait state. if the w ait pin is asserted for additional system clock cycles, w ait states are added until the w ait pin is deasserted (high). chip selects during bus request/bus acknowledge cycles when the cpu relinquishes the address bus to an external peripheral in response to an external bus request ( busreq ), it drives the bus acknowledge pin ( busack ) low . the external peripheral can then drive the address bus (and data bus). the cpu continues to figure 6. w ait state operation example (read operation) t clk w ait t csx_wait x addr[23:0] data[7:0] (input) csx mreq rd in instrd w ait t
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 53 generate chip select signals in response to the address on the bus. external devices cannot access the internal registers of the ez80l92 . bus mode controller the bus mode controller allows the address and data bus timing and signal formats of the ez80l92 to be configured to connect seamlessly with external ez80 ? , z80-, intel-, or motorola-compatible devices. bus modes for each of the chip selects can be configured independently using the chip select bus mode control registers. the number of ez80 ? system clock cycles per bus mode state is also independently programmable. for intel bus mode, multiplexed address and data can be selected in which the lower byte of the address and the data byte both use the data bus, da t a[7:0]. each of the bus modes is explained in more detail in the following sections. ez80 bus mode chip selects configured for ez80 bus mode do not modify the bus signals from the cpu. the timing diagrams for external memory and i/o read and w rite operations are shown in the ac characteristics section on page 204 . the default mode for each chip select is ez80 mode. z80 bus mode chip selects configured for z80 mode modify the ez80 ? bus signals to match the z80 microprocessor address and data bus interface signal format and timing. during read operations, the z80 bus mode employs three states (t1, t2, and t3) as described in t able 14 . during w rite operations, z80 bus mode employs 3 states (t1, t2, and t3) as described in t able 15 . t able 14. z80 bus mode read states state t1 the read cycle begins in state t1. the cpu drives the address onto the address bus and the associated chip select signal is asserted. state t2 during state t2, the rd signal is asserted. depending upon the instruction, either the mreq or iorq signal is asserted. if the external w ait pin is driven low at least one ez80 ? system clock cycle prior to the end of state t2, additional w ait states ( t wait ) are asserted until the w ait pin is driven high. state t3 during state t3, no bus signals are altered. the data is latched by the ez80l92 at the rising edge of the ez80 ? system clock at the end of state t3.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 54 z80 bus mode read and w rite timing is illustrated in figures 7 and 8 . the z80 bus mode states can be configured for 1 to 15 ez80 ? system clock cycles. in the figures, each z80 bus mode state is two ez80 ? system clock cycles in duration. figures 7 and 8 also illustrate the assertion of 1 w ait state ( t wait ) by the external peripheral during each z80 bus mode cycle. t able 15. z80 bus mode w rite states state t1 the write c ycle begins in state t1. the cpu drives the address onto the address bus, the associated chip select signal is asserted. state t2 during state t2, the wr signal is asserted. depending upon the instruction, either the mreq or iorq signal is asserted. if the external w ait pin is driven low at least one ez80 ? system clock cycle prior to the end of state t2, additional w ait states ( t wait ) are asserted until the w ait pin is driven high. state t3 during state t3, no bus signals are altered. figure 7. z80 bus mode read t iming example system clock addr[23:0] data[7:0] csx mreq or iorq rd w ait t clk wr t1 t2 t3
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 55 intel bus mode chip selects configured for intel bus mode modify the ez80 ? bus signals to duplicate a four -state memory transfer similar to that found on intel-style microprocessors. the bus signals and ez80l92 pins are mapped as illustrated in figure 9 . in intel bus mode, the user can select either multiplexed or nonmultiplexed address and data buses. in nonmulti - plexed operation, the address and data buses are separate. in multiplexed operation, the lower byte of the address, addr[7:0], also appears on the data bus, da t a[7:0], during state t1 of the intel bus mode cycle. during multiplexed operation, the lower byte of the address bus also appears on the address bus in addition to the data bus. figure 8. z80 bus mode w rite t iming example system clock addr[23:0] data[7:0] csx mreq or iorq rd w ait t clk wr t1 t2 t3
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 56 intel bus mode (separate address and data buses) during read operations with separate address and data buses, the intel bus mode employs 4 states (t1, t2, t3, and t4) as described in t able 16 . figure 9. intel? bus mode signal and pin mapping t able 16. intel? bus mode read states (separate address and data buses) state t1 the read cycle begins in state t1. the cpu drives the address onto the address bus and the associated chip select signal is asserted. the cpu drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu asserts the rd signal. depending on the instruction, either the mreq or iorq signal is asserted. ez80 bus mode signals (pins) instrd rd wr w ait mreq iorq addr[23:0] data[7:0] multiplexed bus controller addr[7:0] intel bus signal equvalents ale rd wr ready mreq iorq addr[23:0] data[7:0] bus mode controller
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 57 during w rite operations with separate address and data buses, the intel bus mode employs 4 states (t1, t2, t3, and t4) as described in t able 17 . intel bus mode timing is illustrated for a read operation in figure 10 and for a w rite operation in figure 1 1 . if the ready signal (external w ait pin) is driven low prior to the beginning of state t3, additional w ait states ( t wait ) are asserted until the ready signal is driven high. the intel bus mode states can be configured for 2 to 15 ez80 ? system clock cycles. in the figures, each intel? bus mode state is 2 ez80 ? system clock cycles in duration. figures 10 and 1 1 also illustrate the assertion of one w ait state ( t wait ) by the selected peripheral. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one ez80 ? system clock cycle prior to the beginning of state t3, additional w ait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu latches the read data at the beginning of state t4. the cpu deasserts the rd signal and completes the intel bus mode cycle. t able 17. intel? bus mode w rite states (separate address and data buses) state t1 the write cycle begins in state t1. the cpu drives the address onto the address bus, the associated chip select signal is asserted, and the data is driven onto the data bus. the cpu drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu asserts the wr signal. depending on the instruction, either the mreq or iorq signal is asserted. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one ez80 ? system clock cycle prior to the beginning of state t3, additional w ait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu deasserts the wr signal at the beginning of state t4. the cpu holds the data and address buses through the end of t4. the bus cycle is completed at the end of t4. t able 16. intel? bus mode read states (separate address and data buses)
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 58 figure 10. intel? bus mode read t iming example (separate address and data buses) system clock addr[23:0] data[7:0] csx mreq or iorq rd ale t w ait wr ready t1 t2 t3 t4
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 59 figure 1 1. intel? bus mode w rite t iming example (separate address and data buses) e m clock dr[23:0] d ata [7:0] csx mreq or iorq wr ale t w ait rd ready t1 t2 t3 t4
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 60 intel? bus mode (multiplexed address and data bus) during read operations with multiplexed address and data, the intel? bus mode employs 4 states (t1, t2, t3, and t4) as described in t able 18 . during w rite operations with multiplexed address and data, the intel? bus mode employs 4 states (t1, t2, t3, and t4) as described in t able 19 . signal timing for intel? bus mode with multiplexed address and data is illustrated for a read operation in figure 12 and for a w rite operation in figure 13 . in the figures, each t able 18. intel? bus mode read states (multiplexed address and data bus) state t1 the read cycle begins in state t1. the cpu drives the address onto the data bus and the associated chip select signal is asserted. the cpu drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu removes the address from the data bus and asserts the rd signal. depending upon the instruction, either the mreq or iorq signal is asserted. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one ez80 ? system clock cycle prior to the beginning of state t3, additional w ait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu latches the read data at the beginning of state t4. the cpu deasserts the rd signal and completes the intel? bus mode cycle. t able 19. intel? bus mode w rite states (multiplexed address and data bus) state t1 the write cycle begins in state t1. the cpu drives the address onto the data bus and drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu removes the address from the data bus and drives the write data onto the data bus. the wr signal is asserted to indicate a write operation. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one ez80 ? system clock cycle prior to the beginning of state t3, additional w ait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu deasserts the write signal at the beginning of t4 identifying the end of the write operation. the cpu holds the data and address buses through the end of t4. the bus cycle is completed at the end of t4.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 61 intel? bus mode state is 2 ez80 ? system clock cycles in duration. figures 12 and 13 also illustrate the assertion of one w ait state ( t wait ) by the selected peripheral. figure 12. intel? bus mode read t iming example (multiplexed address and data bus) data[7:0] system clock addr[23:0] csx mreq or iorq rd ale t wait wr ready t1 t2 t3 t4
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 62 motorola bus mode chip selects configured for motorola bus mode modify the ez80 ? bus signals to dupli - cate an eight-state memory transfer similar to that found on motorola -style microproces - sors. the bus signals (and ez80l92 i/o pins) are mapped as illustrated in figure 14 . figure 13. intel? bus mode w rite t iming example (multiplexed address and data bus) system clock addr[23:0] data[7:0] csx mreq or iorq wr ale t wait rd ready t1 t2 t3 t4
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 63 during w rite operations, the motorola bus mode employs 8 states (s0, s1, s2, s3, s4, s5, s6, and s7) as described in t able 20 . figure 14. motorola bus mode signal and pin mapping t able 20. motorola bus mode read states state s0 the read cycle starts in state s0. the cpu drives r/ w high to identify a read cycle. state s1 entering state s1, the cpu drives a valid address on the address bus, addr[23:0]. state s2 on the rising edge of state s2, the cpu asserts as and ds . state s3 during state s3, no bus signals are altered. state s4 during state s4, the cpu waits for a cycle termination signal dtack ( wait ), a peripheral signal. if the termination signal is not asserted at least one full cpu clock period prior to the rising clock edge at the end of s4, the cpu inserts wait ( t wait ) states until dtack is asserted. each wait state is a full bus mode cycle. state s5 during state s5, no bus signals are altered. ez80 bus mode signals (pins) instrd rd wr w ait mreq iorq addr[23:0] data[7:0] motorola bus signal equvalents as ds r/w dtack mreq iorq addr[23:0] data[7:0] bus mode controller
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 64 the eight states for a w rite operation in motorola bus mode are described in t able 21 . signal timing for motorola bus mode is illustrated for a read operation in figure 15 and for a w rite operation in figure 16 . in these two figures, each motorola bus mode state is 2 ez80 ? system clock cycles in duration. state s6 during state s6, data from the external peripheral device is driven onto the data bus. state s7 on the rising edge of the clock entering state s7, the cpu latches data from the addressed peripheral device and deasserts as and ds . the peripheral device deasserts dtack at this time. t able 21. motorola bus mode w rite states state s0 the write cycle starts in s0. the cpu drives r/ w high (if a preceding write cycle leaves r/ w low). state s1 entering s1, the cpu drives a valid address on the address bus. state s2 on the rising edge of s2, the cpu asserts as and drives r/ w low. state s3 during s3, the data bus is driven out of the high-impedance state as the data to be written is placed on the bus. state s4 at the rising edge of s4, the cpu asserts ds . the cpu waits for a cycle termination signal dtack ( wait ). if the termination signal is not asserted at least one full cpu clock period prior to the rising clock edge at the end of s4, the cpu inserts wait ( t wait ) states until dtack is asserted. each wait state is a full bus mode cycle. state s5 during s5, no bus signals are altered. state s6 during s6, no bus signals are altered. state s7 upon entering s7, the cpu deasserts as and ds . as the clock rises at the end of s7, the cpu drives r/ w high. the peripheral device deasserts dtack at this time. t able 20. motorola bus mode read states (continued)
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 65 figure 15. motorola bus mode read t iming example system clock addr[23:0] data[7:0] csx mreq or iorq ds as s3 dtack r/w s0 s1 s2 s4 s6 s5 s7
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 66 switching between bus modes each time the bus mode controller must switch from one bus mode to another , there is a one-cycle ez80 ? system clock delay . an extra clock cycle is not required for repeated accesses in any of the bus modes; nor is it required when the ez80l92 switches to ez80 bus mode. the extra clock cycles are not shown in the timing examples. due to the asyn - chronous nature of these bus protocols, the extra delay does not impact peripheral commu - nication. chip select registers chip select x lower bound registers for memory chip selects, the chip select x lower bound register , detailed in t able 22 , defines the lower bound of the address range for which the corresponding memory chip figure 16. motorola bus mode w rite t iming example system clock addr[23:0] data[7:0] csx mreq or iorq ds as s3 dtack r/w s0 s1 s2 s4 s6 s5 s7
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 67 select (if enabled) can be active. for i/o chip selects, this register defines the address to which addr[15:8] is compared to generate an i/o chip select. all chip select lower bound registers reset to 00h . t able 22. chip select x lower bound register s ( cs0_lbr = 00a8h, cs1_lbr = 00abh, cs2_lbr = 00aeh, cs3_lbr = 00b1h) bit 7 6 5 4 3 2 1 0 cs0_lbr reset 0 0 0 0 0 0 0 0 cs1_lbr reset 0 0 0 0 0 0 0 0 cs2_lbr reset 0 0 0 0 0 0 0 0 cs3_lbr reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] cs x _lbr 00hC ffh for memory chip selects ( cs x _io = 0) this byte specifies the lower bound of the chip select address range. the upper byte of the address bus, addr[23:16], is compared to the values contained in these registers for determining whether a memory chip select signal should be generated. for i/o chip selects ( cs x _io = 1) this byte specifies the chip select address value. addr[15:8] is compared to the values contained in these registers for determining whether an i/o chip select signal should be generated.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 68 chip select x upper bound registers for memory chip selects, the chip select x upper bound registers, detailed in t able 23 , defines the upper bound of the address range for which the corresponding chip select (if enabled) can be active. for i/o chip selects, this register produces no ef fect. the reset state for the chip select 0 upper bound register is ffh , while the reset state for the other chip select upper bound registers is 00h . t able 23. chip select x upper bound register s ( cs0_ubr = 00a9h, cs1_ubr = 00ach, cs2_ubr = 00afh, cs3_ubr = 00b2h) bit 7 6 5 4 3 2 1 0 cs0_ubr reset 1 1 1 1 1 1 1 1 cs1_ubr reset 0 0 0 0 0 0 0 0 cs2_ubr reset 0 0 0 0 0 0 0 0 cs3_ubr reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] cs x _ubr 00hC ffh for memory chip selects ( cs x _io = 0) this byte specifies the upper bound of the chip select address range. the upper byte of the address bus, addr[23:16], is compared to the values contained in these registers for determining whether a chip select signal should be generated. for i/o chip selects (csx_io = 1) no effect.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 69 chip select x control registers the chip select x control register , detailed in t able 24 , enables the chip selects, specifies the type of chip select, and sets the number of w ait states. the reset state for the chip select 0 control register is e8h , while the reset state for the 3 other chip select control registers is 00h . t able 24. chip select x control register s ( cs0_ctl = 00aah, cs1_ctl = 00adh, cs2_ctl = 00b0h, cs3_ctl = 00b3h) bit 7 6 5 4 3 2 1 0 cs0_ctl reset 1 1 1 0 1 0 0 0 cs1_ctl reset 0 0 0 0 0 0 0 0 cs2_ctl reset 0 0 0 0 0 0 0 0 cs3_ctl reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r r r note: r/w = read/write; r = read only. bit position v alue description [7:5] cs x _wait * 000 0 wait states are asserted when this chip select is active. 001 1 wait state is asserted when this chip select is active. 010 2 wait states are asserted when this chip select is active. 011 3 wait states are asserted when this chip select is active. 100 4 wait states are asserted when this chip select is active. 101 5 wait states are asserted when this chip select is active. 110 6 wait states are asserted when this chip select is active. 111 7 wait states are asserted when this chip select is active. 4 cs x _io 0 chip select is configured as a memory chip select. 1 chip select is configured as an i/o chip select. 3 csx_en 0 chip select is disabled. 1 chip select is enabled. [2:0] 000 reserved. note: *these wait state settings apply only to the default ez80 bus mode. see table 25.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 70 chip select x bus mode control registers the chip select bus mode register , detailed in t able 25 , configures the chip select for ez80 ? , z80, intel? , or motorola bus modes. changing the bus mode allows the ez80l92 to interface to peripherals based on the z80-, intel? -, or motorola -style asyn - chronous bus interfaces. when a bus mode other than ez80 ? is programmed for a particu - lar chip select, the csx_w ait setting in that chip select control register is ignored. t able 25. chip select x bus mode control register s ( cs0_bmc = 00f0h, cs1_bmc = 00f1h, cs2_bmc = 00f2h, cs3_bmc = 00f3h) bit 7 6 5 4 3 2 1 0 cs0_bmc reset 0 0 0 0 0 0 1 0 cs1_bmc reset 0 0 0 0 0 0 1 0 cs2_bmc reset 0 0 0 0 0 0 1 0 cs3_bmc reset 0 0 0 0 0 0 1 0 cpu access r/w r/w r/w r r/w r/w r/w r/w note: r/w = read/write; r = read only. bit position v alue description [7:6] bus_mode 00 ez80 ? bus mode. 01 z80 bus mode. 10 intel? bus mode. 11 motorola bus mode. 5 ad_mux 0 separate address and data. 1 multiplexed address and dataappears on data bus data[7:0]. 4 0 reserved.
ps013012-1004 preliminary chip selects and wait states ez80l92 mcu product specification 71 [3:0] bus_cycle 0000 not valid. 0001 each bus mode state is 1 ez80 ? clock cycle in duration. 1, 2, 3 0010 each bus mode state is 2 ez80 ? clock cycles in duration. 0011 each bus mode state is 3 ez80 ? clock cycles in duration. 0100 each bus mode state is 4 ez80 ? clock cycles in duration. 0101 each bus mode state is 5 ez80 ? clock cycles in duration. 0110 each bus mode state is 6 ez80 ? clock cycles in duration. 0111 each bus mode state is 7 ez80 ? clock cycles in duration. 1000 each bus mode state is 8 ez80 ? clock cycles in duration. 1001 each bus mode state is 9 ez80 ? clock cycles in duration. 1010 each bus mode state is 10 ez80 ? clock cycles in duration. 1011 each bus mode state is 11 ez80 ? clock cycles in duration. 1100 each bus mode state is 12 ez80 ? clock cycles in duration. 1101 each bus mode state is 13 ez80 ? clock cycles in duration. 1110 each bus mode state is 14 ez80 ? clock cycles in duration. 1111 each bus mode state is 15 ez80 ? clock cycles in duration. notes: 1. setting the bus_cycle to 1 in intel bus mode causes the ale pin to not function properly . 2. use of the external w ait input pin in z80 mode requires that bus_cycle is set to a value greater than 1. 3. these bus_cycle values are not valid in ez80 bus mode. see t able 24. bit position v alue description
ps013012-1004 preliminary watch-dog timer ez80l92 mcu product specification 72 w atch-dog timer watch-dog timer overview the w atch-dog t imer (wdt) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the ez80 ? cpu into unsuitable operating states. the ez80l92 wdt features: ? four programmable time-out periods: 2 18 , 2 22 , 2 25 , and 2 27 clock cycles ? two selectable wdt clock sources: the system clock or the real-time clock source (on-chip 32 khz crystal oscillator or 50/60 hz signal) ? a selectable time-out response: a time-out can be configured to generate either a re - set or a nonmaskable interrupt ( nmi) ? a wdt time-out reset indicator flag figure 17 illustrates the block diagram for the w atch-dog t imer . figure 17. w atch-dog t imer block diagram reset nmi to ez80 cpu 28-bit upcounter control register/ reset register wdt control logic data[7:0] wdt_clk system clock rtc clock time-out compare logic {wdt_period}
ps013012-1004 preliminary watch-dog timer ez80l92 mcu product specification 73 watch-dog timer operation enabling and disabling the wdt the w atch-dog t imer is disabled upon a system reset (reset). t o enable the wdt , the application program must set the wdt_en bit (bit 7) of the wdt_ctl register . when enabled, the wdt cannot be disabled without a reset . t ime-out period selection there are four choices of time-out periods for the wdt2 18 , 2 22 , 2 25 , and 2 27 system clock cycles. the wdt time-out period is defined by the wdt_period field of the wdt_ctl register (wdt_ctl[1:0]). the approximate time-out periods for two dif fer - ent wdt clock sources is listed in t able 26 . reset or nmi generation upon a wdt time-out, the rst_flag in the wdt_ctl register is set to 1. in addition, the wdt can cause a reset or send a nonmaskable interrupt (nmi) signal to the cpu. the default operation is for the wdt to cause a reset . it asserts/deasserts on the rising edge of the clock. the rst_flag bit can be polled by the cpu to determine the source of the reset event. if the nmi_out bit in the wdt_ctl register is set to 1, then upon time-out, the wdt asserts an nmi for cpu processing. the rst_flag bit can be polled by the cpu to t able 26. w atch-dog t imer approximate t ime-out delays clock source divider v alue t ime out delay 32.768 khz crystal oscillator 2 18 8.00 s 32.768 khz crystal oscillator 2 22 128 s 32.768 khz crystal oscillator 2 25 1024 s 32.768 khz crystal oscillator 2 27 4096 s 20mhz system clock 2 18 13.1 ms 20mhz system clock 2 22 209.7 ms 20mhz system clock 2 25 1.68 s 20mhz system clock 2 27 6.71 s 50 mhz system clock 2 18 5.2 ms* 50 mhz system clock 2 22 83.9 ms* 50 mhz system clock 2 25 0.67 s 50 mhz system clock 2 27 2.68 s
ps013012-1004 preliminary watch-dog timer ez80l92 mcu product specification 74 determine the source of the nmi event, provided that the last reset was not caused by the wdt . watch-dog timer registers w atch-dog t imer control register the w atch-dog t imer control register , detailed in t able 27 , is an 8-bit read/w rite regis - ter used to enable the w atch-dog t imer , set the time-out period, indicate the source of the most recent reset , and select the required operation upon wdt time-out. t able 27. w atch-dog t imer control registe r ( wdt_ctl = 0093h) bit 7 6 5 4 3 2 1 0 reset 0 0 0/1 0 0 0 0 0 cpu access r/w r/w r r/w r/w r r/w r/w note: r = read only; r/w = read/write. bit position v alue description 7 wdt_en 0 wdt is disabled. 1 wdt is enabled. when enabled, the wdt cannot be disabled without a full reset. 6 nmi_out 0 wdt time-out resets the cpu. 1 wdt time-out generates a nonmaskable interrupt ( nmi) to the cpu. 5 rst_flag * 0 reset caused by external full-chip reset or zdi reset. 1 reset caused by wdt time-out. this flag is set by the wdt time-out, even if the nmi_out flag is set to 1. the cpu can poll this bit to determine the source of the reset or nmi. [4:3] wdt_clk 00 wdt clock source is system clock. 01 wdt clock source is real-time clock source (32khz on-chip oscillator or 50/60hz input as set by rtc_ctrl[4]) . 10 reserved . 11 reserved . 2 reserved 0 reserved. note: *rst_flag is only cleared by a non-wdt reset.
ps013012-1004 preliminary watch-dog timer ez80l92 mcu product specification 75 w atch-dog t imer reset register the w atch-dog t imer reset register , detailed in t able 28 , is an 8-bit w rite-only register . the w atch-dog t imer is reset when an a5h value followed by 5ah is written to this regis - ter . any amount of time can occur between the writing of the a5h v alue and the 5ah value, so long as the wdt time-out does not occur prior to completion. [1:0] wdt_period 00 wdt time-out period is 2 27 clock cycles. 01 wdt time-out period is 2 25 clock cycles. 10 wdt time-out period is 2 22 clock cycles. 11 wdt time-out period is 2 18 clock cycles. t able 28. w atch-dog t imer reset registe r ( wdt_rr = 0094h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write only. bit position v alue description [7:0] wdt_rr a5h the first write value required to reset the wdt prior to a time- out. 5ah the second write value required to reset the wdt prior to a time-out. if an a5h, 5ah sequence is written to wdt_rr, the wdt timer is reset to its initial count value, and counting resumes. bit position v alue description note: *rst_flag is only cleared by a non-wdt reset.
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 76 programmable reload t imers programmable reload timers overview the ez80l92 features six programmable reload t imers (pr t). each pr t contains a 16- bit downcounter and a 16-bit reload register . in addition, each pr t features a clock pres - caler with four selectable taps for clk 4, clk 16, clk 64, and clk 256. each timer can be individually enabled to operate in either single pass or continuous mode. the timer can be programmed to start, stop, restart from the current value, or restart from the initial value, and generate interrupts to the cpu. four of the programmable reload t imers (timers 0C3) feature a selectable clock source input. the input for these timers can be either the system clock or the real-t ime clock (r tc) source. t imers 0C3 can also be used for event counting, with their inputs received from a gpio port pin. output from timers 4 and 5 can be directed to a gpio port pin. each of the six pr t s available on the ez80l92 can be controlled individually . they do not share the same counters, reload registers, control registers, or interrupt signals. a simpli - fied block diagram of a programmable reload timer is illustrated in figure 18 . figure 18. programmable reload t imer block diagram reload registers {tmrx_rr_h, tmrx_rr_l} data[7:0] data[7:0] data[7:0] tout_en (timers 4C5 only) 16-bit down counter adjustable clock prescaler tmrx_in (timers 0C3 only) tmrx_ctl[3:2] system clock rtc source gpio pin control register tmrx_ctl prt control logic irq to ez80 cpu timer out data registers {tmrx_dr_h, tmrx_dr_l} 2 2
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 77 programmable reload timer operation setting t imer duration there are three factors to consider when determining programmable reload t imer dura - tionclock frequency , clock divider ratio, and initial count value. minimum duration of the timer is achieved by loading 0001h . maximum duration is achieved by loading 0000h , because the timer first rolls over to ffffh and then continues counting down to 0000h . the time-out period of the pr t is returned by the following equation: t o calculate the time-out period with the above equation when using an initial value of 0000h , enter a reload value of 65536 ( ffffh + 1). minimum time-out duration is 4 times longer than the input clock period and is generated by setting the clock divider ratio to 1:4 and the reload value to 0001h . maximum time-out duration is 2 24 (16,777,216) times longer than the input clock period and is generated by setting the clock divider ratio to 1:256 and the reload value to 0000h . single pass mode in single pass mode, when the end-of-count value, 0000h , is reached, counting halts, the timer is disabled, and the prt_en bit resets to 0. t o restart the timer , the cpu must reenable the timer by setting the prt_en b it to 1. an example of a pr t operating in sin - gle pass mode is illustrated in figure 19 . t imer register information is indicated in t able 29 . prt time-out period = clock divider ratio x reload v alue system clock frequency figure 19. prt single pass mode operation example clk clken iowrn t 7:0] irq 0 00 43 2 1 cnth t 7:0] cntl
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 78 continuous mode in continuous mode, when the end-of-count value, 0000h , is reached, the timer auto - matically reloads the 16-bit start value from the t imer reload registers, tmrx_rr_h and tmrx_rr_l. downcounting continues on the next clock edge. in continuous mode, the pr t continues to count until disabled. an example of a pr t operating in continu - ous mode is illustrated in figure 20 . t imer register information is indicated in t able 30 . t able 29. prt single pass mode operation example parameter control register(s) v alue prt enabled tmrx_ctl[0] 1 reload and restart enabled tmrx_ctl[1] 1 prt clock divider = 4 tmrx_ctl[3:2] 00b single pass mode tmrx_ctl[4] 0 prt interrupt enabled tmrx_ctl[6] 1 prt reload value {tmrx_rr_h, tmrx_rr_l} 0004h figure 20. prt continuous mode operation example t able 30. prt continuous mode operation example parameter control register(s) v alue prt enabled tmrx_ctl[0] 1 reload and restart enabled tmrx_ctl[1] 1 prt clock divider = 4 tmrx_ctl[3:2] 00b clk clken iowrn t 7:0] irq 0 04 43 2 1 cnth t 7:0] cntl
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 79 reading the current count v alue the cpu is capable of reading the current count value while the timer is running. this read event does not af fect timer operation. the high byte of the current count value is latched during a read of the low byte. t imer interrupts the timer interrupt flag, prt_irq , is set to 1 whenever the timer reaches its end-of-count value, 0000h , in single pass mode, or when the timer reloads the start value in con - tinuous mode. the interrupt flag is only set when the timer reaches 0000h (or reloads) from 0001h . the timer interrupt flag is not set to 1 when the timer is loaded with the value 0000h , which selects the maximum time-out period. the cpu can be programmed to poll the prt_irq bit for the time-out event. alterna - tively , an interrupt service request signal can be sent to the cpu by setting irq_en to 1. then, when the end-of-count value, 0000h , is reached and prt_irq is set to 1, an inter - rupt service request signal is passed to the cpu. prt_irq is cleared to 0 and the interrupt service request signal is inactivated whenever the cpu reads from the timer control regis - ters, tmrx_ctl. t imer input source selection t imers 0C3 feature programmable input source selection. by default, the input is taken from the ez80l92 s system clock. alternatively , t imers 0C3 can take their input from port input pins pb0 (t imers 0 and 2) or pb1 (t imers 1 and 3). t imers 0C3 can also use the real-t ime clock clock source (50, 60, or 32768hz) as their clock sources. when the timer clock source is the real-t ime clock signal, the timer decrements on the second ris - ing edge of the system clock following the falling edge of the r tc_x out pin. the input source for these timers is set using the t imer input source select register . event counter when t imers 0C3 are configured to take their inputs from port input pins pb0 and pb1, they function as event counters. for event counting, the clock prescaler is bypassed. the pr t counters decrement on every rising edge of the port pin. the port pins must be con - figured as inputs. due to the input sampling on the pins, the event input signal frequency is limited to one-half the system clock frequency . input sampling on the port pins results in continuous mode tmrx_ctl[4] 1 prt interrupt enabled tmrx_ctl[6] 1 prt reload value {tmrx_rr_h, tmrx_rr_l} 0004h t able 30. prt continuous mode operation example (continued) parameter control register(s) v alue
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 80 the pr t counter being updated on the fifth rising edge of the system clock after the rising edge occurs at the port pin. t imer output t wo of the programmable reload t imers (t imers 4 and 5) can be directed to gpio port b output pins ( pb4 and pb5, respectively). t o enable the t imer out feature, the gpio port pin must be configured for alternate functions. after reset, the t imer output feature is dis - abled by default. the gpio output pin toggles each time the pr t reaches its end-of-count value. in continuous mode operation, the disabling of the t imer output feature results in a t imer output signal period that is twice the pr t time-out period. examples of the t imer output operation are illustrated in figure 21 and t able 31 . in these examples, the gpio output is assumed to be low (0) when the t imer output function is enabled. figure 21. prt t imer output operation example t able 31. prt t imer out operation example parameter control register(s) v alue prt enabled tmrx_ctl[0] 1 reload and restart enabled tmrx_ctl[1] 1 prt clock divider = 4 tmrx_ctl[3:2] 00b continuous mode tmrx_ctl[4] 1 prt reload value {tmrx_rr_h, tmrx_rr_l} 0003h clk prt clock (clock 4) iowrn prt count value timer output i/o write to tmrx_ctl enables prt x3 213 21
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 81 programmable reload timer registers each programmable reload timer is controlled using five 8-bit registers. these registers are the t imer control register , t imer reload low byte register , t imer reload high byte register , t imer data low byte register , and t imer data high byte register . the t imer control register can be read or written to. the timer reload registers are w rite- only and are located at the same i/o address as the timer data registers, which are read- only . t imer control registers the t imer control register , detailed in t able 32 , is used to control operation of the timer , including enabling the timer , selecting the clock divider , enabling the interrupt, selecting between continuous and single pass modes, and enabling the auto-reload fea - ture. t able 32. t imer control register s ( tmr0_ctl = 0080h, tmr1_ctl = 0083h, tmr2_ctl = 0086h , t mr3_ctl = 0089h, tmr4_ctl = 008ch, or tmr5_ctl = 008fh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description 7 prt_irq 0 the timer does not reach its end-of-count value. this bit is reset to 0 every time the tmrx_ctl register is read. 1 the timer reaches its end-of-count value. if irq_en is set to 1, an interrupt signal is sent to the cpu. this bit remains 1 until the tmrx_ctl register is read. 6 irq_en 0 timer interrupt requests are disabled. 1 timer interrupt requests are enabled. 5 0 reserved. 4 prt_mode 0 the timer operates in single pass mode. prt_en (bit 0) is reset to 0, and counting stops when the end-of-count value is reached. 1 the timer operates in continuous mode. the timer reload value is written to the counter when the end-of-count value is reached.
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 82 t imer data registerslow byte this read-only register returns the low byte of the current count value of the selected timer . the t imer data registerlow byte, detailed in t able 33 , can be read while the timer is in operation. reading the current count value does not af fect timer operation. t o read the 16-bit data of the current count value, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}, first read the t imer data registerlow byte and then read the t imer data register high byte. the t imer data registerhigh byte value is latched when a read of the t imer data registerlow byte occurs. the t imer data registers and t imer reload registers share the same address space. [3:2] clk_div 00 clock 4 is the timer input source. 01 clock 16 is the timer input source. 10 clock 64 is the timer input source. 11 clock 256 is the timer input source. 1 rst_en 0 the r eload and restart function is disabled. 1 the r eload and restart function is enabled. when a 1 is written to rst_en, the values in the reload registers are loaded into the downcounter and the timer restarts. 0 prt_en 0 the programmable reload timer is disabled. 1 the programmable reload timer is enabled. t able 33. t imer data registerslow byt e ( tmr0_dr_l = 0081h, tmr1_dr_l = 0084h, tmr2_dr_l = 0087h , t mr3_dr_l = 008ah, tmr4_dr_l = 008dh, or tmr5_dr_l = 0090h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] tmr x _dr_l 00hCffh these bits represent the low byte of the 2-byte timer data value, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}. bit 7 is bit 7 of the 16-bit timer data value. bit 0 is bit 0 (lsb) of the 16- bit timer data value. note:
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 83 t imer data registershigh byte this read-only register returns the high byte of the current count value of the selected timer . the t imer data registerhigh byte, detailed in t able 34 , can be read while the timer is in operation. reading the current count value does not af fect timer operation. t o read the 16-bit data of the current count value, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}, first read the t imer data registerlow byte and then read the t imer data register high byte. the t imer data registerhigh byte value is latched when a read of the t imer data registerlow byte occurs. the timer data registers and timer reload registers share the same address space. t able 34. t imer data registershigh byt e ( tmr0_dr_h = 0082h, tmr1_dr_h = 0085h, tmr2_dr_h = 0088h , t mr3_dr_h = 008bh, tmr4_dr_h = 008eh, or tmr5_dr_h = 0091h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] tmr x _dr_h 00hCffh these bits represent the high byte of the 2-byte timer data value, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}. bit 7 is bit 15 (msb) of the 16-bit timer data value. bit 0 is bit 8 of the 16-bit timer data value. note:
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 84 t imer reload registerslow byte the t imer reload registerlow byte, detailed in t able 35 , stores the least significant byte (lsb) of the 2-byte timer reload value. in continuous mode, the timer reload value is reloaded into the timer upon end-of-count. when rst_en (tmrx_ctl[1]) is set to 1 to enable the automatic reload and restart function, the timer reload value is written to the timer on the next rising edge of the clock. the t imer data registers and t imer reload registers share the same address space. t able 35. t imer reload registerslow byt e ( tmr0_rr_l = 0081h, tmr1_rr_l = 0084h, tmr2_rr_l = 0087h , t mr3_rr_l = 008ah, tmr4_rr_l = 008dh, or tmr5_rr_l = 0090h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] tmr x _rr_l 00hCffh these bits represent the low byte of the 2-byte timer reload value, {tmrx_rr_h[7:0], tmrx_rr_l[7:0]}. bit 7 is bit 7 of the 16-bit timer reload value. bit 0 is bit 0 (lsb) of the 16-bit timer reload value. note:
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 85 t imer reload registershigh byte the t imer reload registerhigh byte, detailed in t able 36 , stores the most significant byte (msb) of the 2-byte timer reload value. in continuous mode, the timer reload value is reloaded into the timer upon end-of-count. when rst_en (tmrx_ctl[1]) is set to 1 to enable the automatic reload and restart function, the timer reload value is written to the timer on the next rising edge of the clock. the t imer data registers and t imer reload registers share the same address space. t able 36. t imer reload registershigh byt e ( tmr0_rr_h = 0082h, tmr1_rr_h = 0085h, tmr2_rr_h = 0088h , t mr3_rr_h = 008bh, tmr4_rr_h = 008eh, or tmr5_rr_h = 0091h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] tmr x _rr_h 00hCffh these bits represent the high byte of the 2-byte timer reload value, {tmrx_rr_h[7:0], tmrx_rr_l[7:0]}. bit 7 is bit 15 (msb) of the 16-bit timer reload value. bit 0 is bit 8 of the 16-bit timer reload value. note:
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 86 t imer input source select register the t imer input source select register , detailed in t able 37 , sets the input source for pro - grammable reload t imer 0C3 (tmr0, tmr1, tmr2, tmr3). event frequency must be less than one-half of the system clock frequency . when configured for event inputs through the port pins, the t imers decrement on the fifth system clock rising edge follow - ing the rising edge of the port pin. t able 37. t imer input source select registe r ( tmr_iss = 0092h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:6] tmr3_in 00 the timer counts at the system clock divided by the prescaler. 01 the timer event input is the real-time clock source (32khz or 50/60hzrefer to the real-time clock section on page 88 for details). 10 the timer event input is the gpio port b pin 1. 11 the timer event input is the gpio port b pin 1. [5:4] tmr2_in 00 the timer counts at the system clock divided by the prescaler. 01 the timer event input is the real-time clock source (32khz or 50/60hzrefer to the real-time clock section on page 88 for details). 10 the timer event input is the gpio port b pin 0. 11 the timer event input is the gpio port b pin 0. [3:2] tmr1_in 00 the timer counts at the system clock divided by the prescaler. 01 the timer event input is the real-time clock source (32khz or 50/60hzrefer to the real-time clock section on page 88 for details). 10 the timer event input is the gpio port b pin 1. 11 the timer event input is the gpio port b pin 1.
ps013012-1004 preliminary programmable reload timers ez80l92 mcu product specification 87 [1:0] tmr0_in 00 timer counts at system clock divided by prescaler. 01 timer event input is real-time clock source (32khz or 50/60hzrefer to the real-time clock section on page 88 for details). 10 the timer event input is the gpio port b pin 0. 11 the timer event input is the gpio port b pin 0.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 88 real-t ime clock real-time clock overview the real-t ime clock (r tc) keeps time by maintaining a count of seconds, minutes, hours, day-of-the-week, day-of-the-month, year , and century . the current time is kept in 24-hour format. the format for all count and alarm registers is selectable between binary and binary-coded-decimal (bcd). the calendar operation maintains the correct day of the month and automatically compensates for leap year . a simplified block diagram of the r tc and the associated on-chip, low-power , 32 khz oscillator is illustrated in figure 22 . connections to an external battery supply and 32 khz crystal network are also demon - strated in figure 22 . figure 22. real-t ime clock and 32khz oscillator block diagram rtc_v rtc_x dd v enable clk_sel (rtc_ctrl[4]) 32 khz crystal battery irq addr[15:0] data[7:0] rtc clock system clock dd v dd in c low-power 32 khz oscillator real-time clock to ez80 cpu rtc_x out c r1
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 89 real-time clock alarm the clock can be programmed to generate an alarm condition when the current count matches the alarm set-point registers. alarm registers are available for seconds, minutes, hours, and day-of-the-week. each alarm can be independently enabled. t o generate an alarm condition, the current time must match all enabled alarm values. for example, if the day-of-the-week and hour alarms are both enabled, the alarm only occurs at the specified hour on the specified day . the alarm triggers an interrupt if the interrupt enable bit, int_en, is set. the alarm flag, alarm, and corresponding interrupt to the cpu are cleared by reading the r tc_ctrl register . alarm value registers and alarm control registers can be written at any time. alarm condi - tions are generated when the count value matches the alarm value. the comparison of alarm and count values occurs whenever the r tc count increments (one time every sec - ond). the r tc can also be forced to perform a comparison at any time by writing a 0 to r tc_unlock (r tc_unlock is not required to be changed to a 1 first). real-time clock oscillator and source selection the r tc count is driven by either an external 32 khz o n-chip o scillator or a 50/60 hz power -line frequency input connected to the 32 khz r tc_x out pin. an internal divider compensates for each of these options. the clock source and power -line frequencies are selected in the r tc_ctrl register . w riting to the r tc_ctrl register resets the clock divider . real-time clock battery backup the power supply pin (r tc_v dd ) for the real-t ime clock and associated low-power 32 khz oscillator is isolated from the other power supply pins on the ez80l92 . t o ensure that the r tc continues to keep time in the event of loss of line power to the application, a battery can be used to supply power to the r tc and the oscillator via the r tc_v dd pin. all v ss (ground) pins should be connected together on the printed circuit assembly . real-time clock recommended operation following a reset from a powered-down condition, the counter values of the r tc are undefined and all alarms are disabled. after a reset from a powered-down condition, the following procedure is recommended: ? write to rtc_ctrl to set rtc_unlock and clk_sel ? write values to the rtc count registers to set the current time ? write values to the rtc alarm registers to set the appropriate alarm conditions ? write to rtc_ctrl to clear rtc_unlock; clearing the rtc_unlock bit resets and enables the clock divider
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 90 real-time clock registers the real-time clock registers are accessed via the address and data bus using i/o instruc - tions. r tc_unlock controls access to the r tc count registers. when unlocked (r tc_unlock = 1), the r tc count is disabled and the count registers are read/w rite. when locked (r tc_unlock = 0), the r tc count is enabled and the count registers are read-only . the default, at reset , is for the r tc to be locked. real-t ime clock seconds register this register contains the current seconds count. the value in the r tc_sec register is unchanged by a reset . the current setting of bcd_en determines whether the values in this register are binary (bcd_en = 0) or binary-coded decimal (bcd_en = 1). access to this register is read-only if the r tc is locked and read/w rite if the r tc is unlocked. see t able 38 . t able 38. real-t ime clock seconds registe r ( rtc_sec = 00e0h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] ten_sec 0C5 the tens digit of the current seconds count. [3:0] sec 0C9 the ones digit of the current seconds count. binary operation (bcd_en = 0) bit position v alue description [7:0] sec 00hC 3bh the current seconds count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 91 real-t ime clock minutes register this register contains the current minutes count. see t able 39 . t able 39. real-t ime clock minutes registe r ( rtc_min = 00e1h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] ten_min 0C5 the tens digit of the current minutes count. [3:0] min 0C9 the ones digit of the current minutes count. binary operation (bcd_en = 0) bit position v alue description [7:0] min 00hC 3bh the current minutes count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 92 real-t ime clock hours register this register contains the current hours count. see t able 40 . t able 40. real-t ime clock hours registe r ( rtc_hrs = 00e2h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] ten_hrs 0C2 the tens digit of the current hours count. [3:0] hrs 0C9 the ones digit of the current hours count. binary operation (bcd_en = 0) bit position v alue description [7:0] hrs 00hC 17h the current hours count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 93 real-t ime clock day-of-the-w eek register this register contains the current day-of-the-week count. the r tc_dow register begins counting at 01h . see t able 41 . t able 41. real-t ime clock day-of-the-w eek registe r ( rtc_dow = 00e3h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 x x x x cpu access r r r r r/w* r/w* r/w* r/w* note: x = unchanged by reset; r = read only; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] 0000 reserved. [3:0] dow 1-7 the current day-of-the-week.count. binary operation (bcd_en = 0) bit position v alue description [7:4] 0000 reserved. [3:0] dow 01hC 07h the current day-of-the-week count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 94 real-t ime clock day-of-the-month register this register contains the current day-of-the-month count. the r tc_dom register begins counting at 01h . see t able 42 . t able 42. real-t ime clock day-of-the-month registe r ( rtc_dom = 00e4h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_dom 0C3 the tens digit of the current day-of-the-month count. [3:0] dom 0C9 the ones digit of the current day-of-the-month count. binary operation (bcd_en = 0) bit position v alue description [7:0] dom 01hC 1fh the current day-of-the-month count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 95 real-t ime clock month register this register contains the current month count. see t able 43 . t able 43. real-t ime clock month registe r ( rtc_mon = 00e5h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_mon 0C1 the tens digit of the current month count. [3:0] mon 0C9 the ones digit of the current month count. binary operation (bcd_en = 0) bit position v alue description [7:0] mon 01hC 0ch the current month count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 96 real-t ime clock y ear register this register contains the current year count. see t able 44 . t able 44. real-t ime clock y ear registe r ( rtc_yr = 00e6h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_yr 0C9 the tens digit of the current year count. [3:0] yr 0C9 the ones digit of the current year count. binary operation (bcd_en = 0) bit position v alue description [7:0] yr 00hC 63h the current year count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 97 real-t ime clock century register this register contains the current century count. see t able 45 . t able 45. real-t ime clock century registe r ( rtc_cen = 00e7h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_cen 0C9 the tens digit of the current century count. [3:0] cen 0C9 the ones digit of the current century count. binary operation (bcd_en = 0) bit position v alue description [7:0] cen 00hC 63h the current century count.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 98 real-t ime clock alarm seconds register this register contains the alarm seconds value. see t able 46 . t able 46. real-t ime clock alarm seconds registe r ( rtc_asec = 00e8h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] a ten_sec 0C5 the tens digit of the alarm seconds value. [3:0] asec 0C9 the ones digit of the alarm seconds value. binary operation (bcd_en = 0) bit position v alue description [7:0] asec 00hC 3bh the alarm seconds value.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 99 real-t ime clock alarm minutes register this register contains the alarm minutes value. see t able 47 . t able 47. real-t ime clock alarm minutes registe r ( rtc_amin = 00e9h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] a ten_min 0C5 the tens digit of the alarm minutes value. [3:0] amin 0C9 the ones digit of the alarm minutes value. binary operation (bcd_en = 0) bit position v alue description [7:0] amin 00hC 3bh the alarm minutes value.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 100 real-t ime clock alarm hours register this register contains the alarm hours value. see t able 48 . t able 48. real-t ime clock alarm hours registe r ( rtc_ahrs = 00eah) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] a ten_hrs 0C2 the tens digit of the alarm hours value. [3:0] ahrs 0C9 the ones digit of the alarm hours value. binary operation (bcd_en = 0) bit position v alue description [7:0] ahrs 00hC 17h the alarm hours value.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 101 real-t ime clock alarm day-of-the-w eek register this register contains the alarm day-of-the-week value. see t able 49 . t able 49. real-t ime clock alarm day-of-the-w eek registe r ( rtc_adow = 00ebh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 x x x x cpu access r r r r r/w* r/w* r/w* r/w* note: x = unchanged by reset; r = read only; r/w* = read-only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] 0000 reserved. [3:0] adow 1-7 the alarm day-of-the-week.value. binary operation (bcd_en = 0) bit position v alue description [7:4] 0000 reserved. [3:0] adow 01hC 07h the alarm day-of-the-week value.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 102 real-t ime clock alarm control register this register contains alarm enable bits for the real-time clock. the r tc_actrl register is cleared by a reset . see t able 50 . real-t ime clock control register this register contains control and status bits for the real-time clock. some bits in the r tc_ctrl register are cleared by a reset . the alarm flag and associated interrupt (if int_en is enabled) are cleared by reading this register . the alarm flag is updated by clearing (locking) r tc_unlock or by an increment of the r tc count. w riting to the r tc_ctrl register also resets the r tc count prescaler allowing the r tc to be synchro - nized to another time source. slp_w ake indicates if an r tc alarm condition initiated the cpu recovery from sleep mode. this bit can be checked after reset to determine if a sleep-mode recovery is caused by the r tc. slp_w ake is cleared by a read of the r tc_ctrl register . setting bcd_en causes the r tc to use bcd counting in all registers including the alarm set points. clk_sel and freq_sel select the r tc clock source. if the 32 khz crystal option is selected the oscillator is enabled and the internal prescaler is set to divide by 32768. if the power -line frequency option is selected, the prescale value is set by freq_sel, and the 32 khz oscillator is disabled. see t able 51 . t able 50. real-t ime clock alarm control registe r ( rtc_actrl = 00ech) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write; r = read only. bit position v alue description [7:4] 0000 reserved. 3 adow_en 0 the day-of-the-week alarm is disabled. 1 the day-of-the-week alarm is enabled. 2 ahrs_en 0 the hours alarm is disabled. 1 the hours alarm is enabled. 1 amin_en 0 the minutes alarm is disabled. 1 the minutes alarm is enabled. 0 asec_en 0 the seconds alarm is disabled. 1 the seconds alarm is enabled.
ps013012-1004 preliminary real-time clock ez80l92 mcu product specification 103 t able 51. real-t ime clock control registe r ( rtc_ctrl = 00edh) bit 7 6 5 4 3 2 1 0 reset x 0 x x x x 0/1 0 cpu access r r/w r/w r/w r/w r r r/w note: x = unchanged by reset; r = read-only; r/w = read/write. bit position v alue description 7 alarm 0 alarm interrupt is inactive. 1 alarm interrupt is active. 6 int_en 0 interrupt on alarm condition is disabled. 1 interrupt on alarm condition is enabled. 5 bcd_en 0 rtc count and alarm value registers are binary. 1 rtc count and alarm value registers are binary-coded decimal (bcd). 4 clk_sel 0 rtc clock source is crystal oscillator output (32768 hz). on-chip 32768hz oscillator is enabled. 1 rtc clock source is power-line frequency input. on-chip 32768 hz oscillator is disabled. 3 freq_sel 0 power-line frequency is 60 hz. 1 power-line frequency is 50 hz. 2 0 reserved. 1 slp_wake 0 rtc does not generate a sleep-mode recovery reset. 1 rtc alarm generates a sleep-mode recovery reset. 0 rtc_unlock 0 rtc count registers are locked to prevent write access. rtc counter is enabled. 1 rtc count registers are unlocked to allow write access. rtc counter is disabled.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 104 universal asynchronous receiver/ t ransmitter the uar t module implements all of the logic required to support various asynchronous communications protocols. the module also implements two separate 16-byte-deep fifos for both transmission and reception. a block diagram of the uar t is illustrated in figure 23 . the uar t module provides the following asynchronous communication protocol-related features and functions: ? 5-, 6-, 7-, or 8-bit data transmission ? even/odd or no parity bit generation and detection ? start and stop bit generation and detection (supports up to two stop bits) ? line break detection and generation ? receiver overrun and framing errors detection ? logic and associated i/o to provide modem handshake capability uart functional description the uar t function implements: figure 23. uart block diagram system clock i/o address data receive buffer transmit buffer modem control logic interrupt signal to ez80 cpu uart control interface and baud rate generator rxd0/rxd1 txd0/txd1 cts0/cts1 rts0/rts1 dsr0/dsr1 dtr0/dtr1 dcd0/dcd1 ri0/ri1
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 105 ? the transmitter and associated control logic ? the receiver and associated control logic ? the modem interface and associated logic uart t ransmitter the transmitter block controls the data transmitted on the t x d output. it implements the fifo, accessed through the uar tx_thr register , the transmit shift register , the parity generator , and control logic for the transmitter to control parameters for the asynchronous communication protocol. the uar tx_thr is a w rite-only register . the processor writes the data byte to be trans - mitted into this register . in the fifo mode, up to 16 data bytes can be written via the uar tx_thr register . the data byte from the fifo is transferred to the transmit shift reg - ister at the appropriate time and transmitted out on t x d output. after sync_reset , the uar tx_thr register is empty . therefore, the t ransmit holding register empty (thre) bit (bit 5 of the uart x _lsr register) is 1 and an interrupt is sent to the processor (if interrupts are enabled). the processor can reset this interrupt by loading data into the uar tx_thr register , which clears the transmitter interrupt. the transmit shift register places the byte to be transmitted on the t x d signal serially . the least-significant bit of the byte to be transmitted is shifted out first and the most significant bit is shifted out last. the control logic within the block adds the asynchronous communi - cation protocol bits to the data byte being transmitted. the transmitter block obtains the parameters for the protocol from the bits programmed via the uar tx_lctl register . the t x d output is set to 1 if the transmitter is idle (it does not contain any data to be transmit - ted). the transmitter operates with the baud rate generator (brg) clock. the data bits are placed on the t x d output one time every 16 brg clock cycles. the transmitter block also implements a parity generator that attaches the parity bit to the byte, if programmed. uart receiver the receiver block controls the data reception from the r x d signal. the receiver block implements a receiver shift register , receiver line error condition monitoring logic and receiver data ready logic. it also implements the parity checker . the uar tx_rbr is a read-only register of the module. the processor reads received data from this register . the condition of the uar tx_rbr register is monitored by the dr bit (bit 0 of the uar tx_lsr register). the dr bit is 1 when a data byte is received and transferred to the uar tx_rbr register from the receiver shift register . the dr bit is reset only when the processor reads all of the received data bytes. if the number of bits received is less than eight, the unused most significant bits of the data byte read are 0. the receiver uses the clock from the brg for receiving the data. this clock must be 16 times the appropriate baud rate. the receiver synchronizes the shift clock on the falling
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 106 edge of the r x d input start bit. it then receives a complete byte according to the set parameters. the receiver also implements logic to detect framing errors, parity errors, overrun errors, and break signals. uart modem control the modem control logic provides two outputs and four inputs for handshaking with the modem. any change in the modem status inputs, except ri , is detected and an interrupt can be generated. for ri , an interrupt is generated only when the trailing edge of the ri is detected. the module also provides loop mode for self-diagnostics. uart interrupts there are five dif ferent sources of interrupts from the uar t . the five sources of inter - rupts are: ? transmitter ? receiver (three different interrupts) ? modem status uart t ransmitter interrupt the transmitter interrupt is generated if there is no data available for transmission. this interrupt can be disabled using the individual interrupt enable bit or cleared by writing data into the uar tx_thr register . uart receiver interrupts a receiver interrupt can be generated by three possible sources. the first source, a receiver data ready , indicates that one or more data bytes are received and are ready to be read. this interrupt is generated if the number of bytes in the receiver fifo is greater than or equal to the trigger level. if the fifo is not enabled, the interrupt is generated if the receive buf fer contains a data byte. this interrupt is cleared by reading the uar tx_rbr. the second interrupt source is the receiver time-out. a receiver time-out interrupt is gener - ated when there are fewer data bytes in the receiver fifo than the trigger level and there are no reads and w rites to or from the receiver fifo for four consecutive byte times. when the receiver time-out interrupt is generated, it is cleared only after emptying the entire receive fifo. the first two interrupt sources from the receiver (data ready and time-out) share an inter - rupt enable bit. the third source of a receiver interrupt is a line status error , indicating an error in byte reception. this error may result from: ? incorrect received parity
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 107 ? incorrect framing; that is, the stop bit is not detected by receiver at the end of the byte ? receiver over run condition ? a break condition being detected on the receive data input an interrupt due to one of the above conditions is cleared when the uar tx_lsr register is read. in fifo mode, a line status interrupt is generated only after the received byte with an error reaches the top of the fifo and is ready to be read. a line status interrupt is activated (provided this interrupt is enabled) as long as the read p ointer of the receiver fifo points to the location of the fifo that contains a byte with the error . the interrupt is immediately cleared when the uar tx_lsr register is read. the err bit of the uar tx_lsr register is active as long as an erroneous byte is present in the receiver fifo. uart modem status interrupt the modem status interrupt is generated if there is any change in state of the modem status inputs to the uar t . this interrupt is cleared when the processor reads the uar tx_msr register . uart recommended usage the following is the standard sequence of events that occur in the ez80l92 using the uar t . a description of each follows. 1. module reset. 2. control transfers to configure uar t operation. 3. data transfers. module reset . upon reset, all internal registers are set to their default values. all com - mand status registers are programmed with their default values, and the fifos are flushed. control transfers . based on the requirements of the application, the data transfer baud rate is determined and the brg is configured to generate a 16x clock frequency . inter - rupts are disabled and the communication control parameters are programmed in the uar tx_lctl register . the fifo configuration is determined and the receive trigger lev - els are set in the uar tx_fctl register . the status registers, uar tx_lsr and uar tx_msr, are read, and ensure that none of the interrupt sources are active. the inter - rupts are enabled (except for the transmit interrupt) and the application is ready to use the module for transmission/reception. data transferstransmit . t o transmit data, the application enables the transmit inter - rupt. an interrupt is immediately expected in response. the application reads the
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 108 uar tx_iir register and determines that the interrupt occurs due to an empty uar tx_thr register . when the application determines this occurrence, the application writes the transmit data bytes to the uar tx_thr register . the number of bytes that the application writes depends on whether or not the fifo is enabled. if the fifo is enabled, the application can write 16 bytes at a time. if not, the application can write one byte at a time. as a result of the first w rite, the interrupt is deactivated. the processor then waits for the next interrupt. when the interrupt is raised by the uar t module, the processor repeats the same process until it exhausts all of the data for transmission. t o control and check the modem status, the application sets up the modem by writing to the uar tx_mctl register and reading the uar tx_mctl register before starting the process mentioned above. data transfersreceive . the receiver is always enabled, and it continually checks for the start bit on the r x d input signal. when an interrupt is raised by the uar t module, the application reads the uar tx_iir register and determines the cause for the interrupt. if the cause is a line status interrupt, the application reads the uar tx_lsr register , reads the data byte and then can discard the byte or take other appropriate action. if the interrupt is caused by a receive-data-ready condition, the application alternately reads the uar tx_lsr and uar tx_rbr registers and removes all of the received data bytes. it reads the uar tx_lsr register before reading the uar tx_rbr register to determine that there is no error in the received data. t o control and check modem status, the application sets up the modem by writing to the uar tx_mctl register and reading the uar tx_msr register before starting the process mentioned above. poll mode transfers . when interrupts are disabled, all data transfers are referred to as poll mode transfers. in poll mode transfers, the application must continually poll the uar tx_lsr register to transmit or receive data without enabling the interrupts. the same holds true for the uar tx_msr register . if the interrupts are not enabled, the data in the uar tx_iir register cannot be used to determine the cause of interrupt. baud rate generator the baud rate generator consists of a 16-bit downcounter , two registers, and associated decoding logic. the initial value of the baud rate generator is defined by the two brg divisor latch registers, {uar tx_brg_h, uar tx_brg_l}. at the rising edge of each system clock, the brg decrements until it reaches the value 0001h . on the next system clock rising edge, the brg reloads the initial value from {uar tx_brg_h, uar tx_brg_l) and outputs a pulse to indicate the end-of-count. calculate the uar t data rate with the following equation: uart data rate (bits/s) = system clock frequency 16 x (uar t baud rate generator divisor)
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 109 upon reset , the 16-bit brg divisor value resets to 0002h . a minimum brg divisor value of 0001h is also valid, and ef fectively bypasses the brg. a software w rite to either the low- or high-byte registers for the brg divisor latch causes both the low and high bytes to load into the brg counter , and causes the count to restart. the divisor registers can only be accessed if bit 7 of the uar t line control register ( uar t x _lctl ) is set to 1. after reset, this bit is reset to 0. recommended usage of the baud rate generator the following is the normal sequence of operations that should occur after the ez80l92 is powered on to configure the baud rate generator: ? set uartx_lctl[7] to 1 to enable access of the brg divisor registers ? program the uartx_brg_l and uartx_brg_h registers ? clear uartx_lctl[7] to 0 to disable access of the brg divisor registers brg control registers uart baud rate generator registerslow and high bytes the registers hold the low and high bytes of the 16-bit divisor count loaded by the pro - cessor for uar t baud rate generation. the 16-bit clock divisor value is returned by {uar t x _brg_h, uar t x _brg_l}, where x is either 0 or 1 to identify the two available uar t devices. upon reset , the 16-bit brg divisor value resets to 0002h . the initial 16-bit divisor value must be between 0002h and ffffh as the values 0000h and 0001h are invalid, and proper operation is not guaranteed. as a result, the minimum brg clock divisor ratio is 2. a w rite to either the low- or high-byte registers for the brg divisor latch causes both bytes to be loaded into the brg counter . the count is then restarted. bit 7 of the associated uar t line control register (uar t x _lctl) must be set to 1 to access this register . see t ables 52 and 53 . refer to the uar t line control registers (uar tx_lctl) on page 1 15 for more information. the uar tx_brg_l registers share the same address space with the uar tx_rbr and uar tx_thr registers. the uar tx_brg_h registers share the same address space with the uar tx_ier registers. bit 7 of the associated uar t line control register (uar tx_lctl) must be set to 1 to enable access to the brg registers. note:
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 110 uart registers after a reset , all uar t registers are set to their default values. any w rites to unused registers or register bits are ignored and reads return a value of 0. for compatibility with future revisions, unused bits within a register should always be written with a value of 0. read/w rite attributes, reset conditions, and bit descriptions of all of the uar t registers are provided in this section. uart t ransmit holding registers if less than eight bits are programmed for transmission, the lower bits of the byte written to this register are selected for transmission. the transmit fifo is mapped at this address. the user can write up to 16 bytes for transmission at one time to this address if the fifo is enabled by the application. if the fifo is disabled, this buf fer is only one byte deep. t able 52. uart baud rate generator registerslow byt e ( uart0_brg_l = 00c0h, uart1_brg_l = 00d0h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 1 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:0] uar t x _brg_l 00hC ffh these bits represent the low byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {uart x _brg_h, uart x _brg_l}. t able 53. uart baud rate generator registershigh byt e ( uart0_brg_h = 00c1h, uart1_brg_h = 00d1h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:0] uar t x _brg_h 00hC ffh these bits represent the high byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {uart x _brg_h, uart x _brg_l}.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 111 these registers share the same address space as the uar tx_rbr and uar tx_brg_l registers. see t able 54 . uart receive buffer registers the bits in this register reflect the data received. if less than eight bits are programmed for receive, the lower bits of the byte reflect the bits received whereas upper unused bits are 0. the receive fifo is mapped at this address. if the fifo is disabled, this buf fer is only one byte deep. these registers share the same address space as the uar tx_thr and uar tx_brg_l registers. see t able 55 . t able 54. uart t ransmit holding register s ( uart0_thr = 00c0h, uart1_thr = 00d0h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] t x d 00hC ffh transmit data byte. t able 55. uart receive buffer register s ( uart0_rbr = 00c0h, uart1_rbr = 00 d0h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] r x d 00hC ffh receive data byte.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 112 uart interrupt enable registers the uar tx_ier register is used to enable and disable the uar t interrupts. the uar tx_ier registers share the same i/o addresses as the uar tx_brg_h registers. see t able 56 . t able 56. uart interrupt enable register s ( uart0_ier = 00c1h, uart1_ier = 00d1h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r/w r/w r/w r/w note: r = read only.; r/w = read/write. bit position v alue description [7:4] 0000 reserved 3 miie 0 modem interrupt on edge detect of status inputs is disabled. 1 modem interrupt on edge detect of status inputs is enabled. 2 lsie 0 line status interrupt is disabled. 1 line status interrupt is enabled for receive data errors: incorrect parity bit received, framing error, overrun error, or break detection. 1 tie 0 transmit interrupt is disabled. 1 transmit interrupt is enabled. interrupt is generated when the transmit fifo/buffer is empty indicating no more bytes available for transmission. 0 rie 0 receive interrupt is disabled. 1 receive interrupt and receiver time-out interrupt are enabled. interrupt is generated if the fifo/buffer contains data ready to be read or if the receiver times out.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 113 uart interrupt identification registers the read-only uar tx_iir register allows the user to check whether the fifo is enabled and the status of interrupts. these registers share the same i/o addresses as the uar tx_fctl registers. see t ables 57 and 58 . t able 57. uart interrupt identification register s ( uart0_iir = 00c2h, uart1_iir = 00d2h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 1 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:6] fsts 00 fifo is disabled. 11 fifo is enabled. [5:4] 00 reserved [3:1] insts 000C 110 interrupt status code the code indicated in these three bits is valid only if intbit is 1. if two internal interrupt sources are active and their respective enable bits are high, only the higher priority interrupt is seen by the application. the lower-priority interrupt code is indicated only after the higher-priority interrupt is serviced. t able 58 lists the interrupt status codes. 0 intbit 0 there is an active interrupt source within the uart. 1 there is not an active interrupt source within the uart. t able 58. uart interrupt status codes insts v alue priority interrupt t ype 011 highest receiver line status 010 second receive data ready or trigger level 110 third character time-out 001 fourth transmit buffer empty 000 lowest modem status
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 114 uart fifo control registers this register is used to monitor trigger levels, clear fifo pointers, and enable or disable the fifo. the uar tx_fctl registers share the same i/o addresses as the uar tx_iir registers. see t able 59 . t able 59. uart fifo control register s ( uart0_fctl = 00c2h, uart1_fctl = 00d2h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description [7:6] trig 00 receive fifo trigger level set to 1. receive data interrupt is generated when there is 1 byte in the fifo. valid only if fifo is enabled. 01 receive fifo trigger level set to 4. receive data interrupt is generated when there are 4 bytes in the fifo. valid only if fifo is enabled. 10 receive fifo trigger level set to 8. receive data interrupt is generated when there are 8 bytes in the fifo. valid only if fifo is enabled. 11 receive fifo trigger level set to 14. receive data interrupt is generated when there are 14 bytes in the fifo. valid only if fifo is enabled. [5:3] 000 reserved. 2 clrtxf 0 no effect. 1 clear the transmit fifo and reset the transmit fifo pointer. valid only if the fifo is enabled. 1 clrrxf 0 no effect. 1 clear the receive fifo, clear the receive error fifo, and reset the receive fifo pointer. valid only if the fifo is enabled. 0 fifoen 0 transmit and receive fifos are disabled. transmit and receive buffers are only 1 byte deep. 1 transmit and receive fifos are enabled.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 115 uart line control registers this register is used to control the communication control parameters. see t ables 60 and 61 . t able 60. uart line control register s ( uart0_lctl = 00c3h, uart1_lctl = 00d3h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description 7 dlab 0 access to the uart registers at i/o addresses uartx_rbr, uartx_thr, and uartx_ier is enabled. 1 access to the baud rate generator registers at i/o addresses uartx_brg_l and uartx_brg_h is enabled. 6 sb 0 do not send a break signal. 1 send break uart sends continuous zeroes on the transmit output from the next bit boundary. the transmit data in the transmit shift register is ignored. after forcing this bit high, the t x d output is 0 only after the bit boundary is reached. just before forcing t x d to 0, the transmit fifo is cleared. any new data written to the transmit fifo during a break should be written only after the thre bit of uartx_lsr register goes high. this new data is transmitted after the uart recovers from the break. after the break is removed, the uart recovers from the break for the next brg edge. 5 fpe 0 do not force a parity error. 1 force a parity error. when this bit and the party enable bit (pen) are both 1, an incorrect parity bit is transmitted with the data byte. 4 eps 0 use odd parity for transmission. the total number of 1 bits in the transmit data plus parity bit is odd. 1 use even parity for transmission. the total number of 1 bits in the transmit data plus parity bit is even.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 116 3 pen 0 parity bit transmit and receive is disabled. 1 parity bit transmit and receive is enabled. for transmit, a parity bit is generated and transmitted with every data character. for receive, the parity is checked for every incoming data character. [2:0] char 000C 111 uart character parameter selection see table 61 for a description of the values. t able 61. uart character parameter definition char[2:0] character length (tx/rx data bits) stop bits (tx stop bits) 000 5 1 001 6 1 010 7 1 01 1 8 1 100 5 2 101 6 2 1 10 7 2 1 1 1 8 2 bit position v alue description
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 117 uart modem control registers this register is used to control and check the modem status. see t able 62 . t able 62. uart modem control register s ( uart0_mctl = 00c4h, uart1_mctl = 00d4h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r/w r/w r/w r/w r/w note: r = read only.; r/w = read/write. bit position v alue description [7:5] 000b reserved. 4 loop 0 loop back mode is not enabled. 1 loop back mode is enabled. the uart operates in internal loop back mode. the transmit data output port is disconnected from the internal transmit data output and set to 1. the receive data input port is disconnected and internal receive data is connected to internal transmit data. the modem status input ports are disconnected and the four bits of the modem control register are connected as modem status inputs. the two modem control output ports (out1&2) are set to their inactive state 3 out2 0C1 no function in normal operation. in loop back mode, this bit is connected to the dcd bit in the uart status register. 2 out1 0C1 no function in normal operation. in loop back mode, this bit is connected to the ri bit in the uart status register. 1 rts 0C1 request to send. in normal operation, the rts output port is the inverse of this bit. in loop back mode, this bit is connected to the cts bit in the uart status register. 0 dtr 0C1 data terminal ready. in normal operation, the dtr output port is the inverse of this bit. in loop back mode, this bit is connected to the dsr bit in the uart status register.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 118 uart line status registers this register is used to show the status of uar t interrupts and registers. see t able 63 . t able 63. uart line status register s ( uart0_lsr = 00c5h, uart1_lsr = 00 d5h) bit 7 6 5 4 3 2 1 0 reset 0 1 1 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description 7 err 0 always 0 when operating with the fifo disabled. with the fifo enabled, this bit is reset when the uartx_lsr register is read and there are no more bytes with error status in the fifo. 1 error detected in the fifo. there is at least 1 parity, framing or break indication error in the fifo. 6 temt 0 transmit holding register/fifo is not empty or transmit shift register is not empty or transmitter is not idle. 1 transmit holding register/fifo and transmit shift register are empty; and the transmitter is idle. this bit cannot be set to 1 during the break condition. this bit only becomes 1 after the break command is removed. 5 thre 0 transmit holding register/fifo is not empty. 1 transmit holding register/fifo is empty. this bit cannot be set to 1 during the break condition. this bit only becomes 1 after the break command is removed. 4 bi 0 receiver does not detect a break condition. this bit is reset to 0 when the uartx_lsr register is read. 1 receiver detects a break condition on the receive input line. this bit is 1 if the duration of break condition on the receive data is longer than one character transmission time, the time depends on the programming of the uartx_lsr register. in case of fifo only one null character is loaded into the receiver fifo with the framing error. the framing error is revealed to the ez80 ? whenever that particular data is read from the receiver fifo.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 119 3 fe 0 no framing error detected for character at the top of the fifo. this bit is reset to 0 when the uartx_lsr register is read. 1 framing error detected for the character at the top of the fifo. this bit is set to 1 when the stop bit following the data/ parity bit is logic 0. 2 pe 0 the received character at the top of the fifo does not contain a parity error. this bit is reset to 0 when the uartx_lsr register is read. 1 the received character at the top of the fifo contains a parity error. 1 oe 0 the received character at the top of the fifo does not contain an overrun error. this bit is reset to 0 when the uartx_lsr register is read. 1 overrun error is detected. if the fifo is not enabled, this indicates that the data in the receive buffer register was not read before the next character was transferred into the receiver buffer register. if the fifo is enabled, this indicates the fifo was already full when an additional character was received by the receiver shift register. the character in the receiver shift register is not put into the receiver fifo. 0 dr 0 this bit is reset to 0 when the uartx_rbr register is read or all bytes are read from the receiver fifo. 1 data ready. if the fifo is not enabled, this bit is set to 1 when a complete incoming character is transferred into the receiver buffer register from the receiver shift register. if the fifo is enabled, this bit is set to 1 when a character is received and transferred to the receiver fifo. bit position v alue description
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 120 uart modem status registers this register is used to show the status of the uar t signals. see t able 64 . t able 64. uart modem status register s ( uart0_msr = 00c6h, uart1_msr = 00 d6h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: r = read only. bit position v alue description 7 dcd 0C1 data carrier detect in normal mode, this bit reflects the inverted state of the dcdx input pin. in loop back mode, this bit reflects the value of the uartx_mctl[3] = out2. 6 ri 0C1 ring indicator in normal mode, this bit reflects the inverted state of the rix input pin. in loop back mode, this bit reflects the value of the uartx_mctl[2] = out1. 5 dsr 0C1 data set ready in normal mode, this bit reflects the inverted state of the dsrx input pin. in loop back mode, this bit reflects the value of the uartx_mctl[0] = dtr. 4 cts 0C1 clear to send in normal mode, this bit reflects the inverted state of the ctsx input pin. in loop back mode, this bit reflects the value of the uartx_mctl[1] = rts. 3 ddcd 0C1 delta status change of dcd this bit is set to 1 whenever the dcdx pin changes state. this bit is reset to 0 when the uartx_msr register is read. 2 teri 0C1 trailing edge change on ri . this bit is set to 1 whenever a falling edge is detected on the rix pin. this bit is reset to 0 when the uartx_msr register is read. 1 ddsr 0C1 delta status change of dsr this bit is set to 1 whenever the dsrx pin changes state. this bit is reset to 0 when the uartx_msr register is read. 0 dcts 0C1 delta status change of cts this bit is set to 1 whenever the ctsx pin changes state. this bit is reset to 0 when the uartx_msr register is read.
ps013012-1004 preliminary universal asynchronous receiver/transmitter ez80l92 mcu product specification 121 uart scratch pad registers the uar tx_spr register can be used by the system as a general-purpose read/w rite reg - ister . see t able 65 . t able 65. uart scratch pad register s ( uart0_spr = 00c7h, uart1_spr = 00d7h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] spr 00hC ffh uart scratch pad register is available for use as a general- purpose read/write register.
ps013012-1004 preliminary infrared encoder/decoder ez80l92 mcu product specification 122 infrared encoder/decoder the ez80l92 mcu contains a uar t to infrared encoder/decoder (endec). the infrared encoder/decoder is integrated with the on-chip uar t0 to allow easy communication between the ez80 ? cpu and irda physical layer specification v ersion 1.3 compliant infrared transceivers as illustrated in figure 24 . infrared communication provides secure, reliable, high-speed, low-cost, point-to-point communication between pcs, pdas, mobile telephones, printers and other infrared enabled devices. functional description when the infrared encoder/decoder is enabled, the transmit data from the on-chip uar t is encoded as digital signals in accordance with the irda standard and output to the infra - red transceiver . likewise, data received from the infrared transceiver is decoded by the infrared encoder/decoder and passed to the uar t . communication is half-duplex mean - ing that simultaneous data transmission and reception is not allowed. the baud rate is set by the uar t baud rate generator and supports irda standard baud rates from 9600 bits/s to 1 15.2 kbps. higher baud rates are possible, but do not meet irda specifications. the uar t must be enabled to use the infrared encoder/decoder . refer to figure 24. infrared system block diagram ez80l92 to ez80 cpu system clock uart0 rxd txd rxd txd ir_rxd ir_txd baud rate clock infrared encoder/decoder interrupt signal i/o address data i/o address data infrared transceiver
ps013012-1004 preliminary infrared encoder/decoder ez80l92 mcu product specification 123 the section covering the universal asynchronous receiver/t ransmitter , on page 104 , for more information about the uar t and its baud rate generator . transmit the data to be transmitted via the ir transceiver is first sent to uar t0. the uar t trans - mit signal ( t x d ) and baud rate clock are used by the infrared encoder/decoder to gener - ate the modulation signal (ir_txd) that drives the infrared transceiver . each uar t b it is 16-clocks wide. if the data to be transmitted is a logical 1 (high), the ir_txd signal remains low (0) for the full 16-clock period. if the data to be transmitted is a logical 0, a 3-clock high (1) pulse is output following a 7-clock low (0) period. following the 3- clock high pulse, a 6-clock low pulse completes the full 16-clock data period. data trans - mission is illustrated in figure 25 . during data transmission, the ir receive function should be disabled by clearing the ir_rxen bit in the ir_ctl reg to 0. this prevents transmitter to receiver cross-talk. receive data received from the ir transceiver via the ir_rxd signal is decoded by the infrared encoder/decoder and passed to the uar t . the ir_rxen bit in the ir_ctl register must be set to enable the receiver decoder . the sir data format uses half duplex communica - tion therefore the uar t should not be allowed to transmit while the receiver decoder is enabled. the uar t baud rate clock is used by the infrared encoder/decoder to generate the demodulated signal ( r x d ) that drives the uar t . each uar t bit is 16-clocks wide. if the data to be received is a logical 1 (high), the ir_rxd signal remains high (1) for the full 16-clock period. if the data to be received is a logical 0, a 3-clock low (0) pulse is figure 25. infrared data t ransmission 16-clock period 3-clock pulse 7-clock delay baud rate clock uart_txd start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 ir_txd
ps013012-1004 preliminary infrared encoder/decoder ez80l92 mcu product specification 124 output following a 7-clock high (1) period. following the 3-clock low pulse, is a 6-clock high pulse to complete the full 16-clock data period. data transmission is illustrated in figure 26 . jitter due to the inherent sampling of the received ir_rxd signal by the bit rate clock, some jitter can be expected on the first bit in any sequence of data. however , all subsequent bits in the received data stream are a fixed 16-clock periods wide. infrared encoder/decoder signal pins the infrared encoder/decoder signal pins (ir_txd and ir_rxd) are multiplexed with general-purpose i/o (gpio) pins. these gpio pins must be configured for alternate func - tion operation for the infrared encoder/decoder to operate. the remaining six uar t0 pins ( cts0 , dcd0 , dsr0 , dtr0 , r ts0 and ri0 ) are not required for use with the infrared encoder/decoder . the uar t0 modem status interrupt should be disabled to prevent unwanted interrupts from these pins. the gpio pins corre - sponding to these six unused uar t0 pins can be used for inputs, outputs, or interrupt sources. recommended gpio port d control register settings are provided in t able 66 . refer to the section covering the general-purpose input/output , on page 39 for additional information about setting the gpio port modes figure 26. infrared data reception 16-clock period 16-clock period 16-clock period 16-clock period 1.6 s min. pulse 8-clock delay baud rate clock ir_rxd start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 uart_rxd 16-clock period
ps013012-1004 preliminary infrared encoder/decoder ez80l92 mcu product specification 125 loopback testing both internal and external loopback testing can be accomplished with the endec on the ez80l92 . internal loopback testing is enabled by setting the loop_back bit to 1. dur - ing internal loopback, ir_txd output signal is inverted and connected on-chip to the ir_rxd input. external loopback testing of the of f-chip irda transceiver may be accomplished by transmitting data from the uar t while the receiver is enabled (ir_rxen set to 1). infrared encoder/decoder register after a reset , the infrared encoder/decoder register is set to its default value. any w rites to unused register bits are ignored and reads return a value of 0. unused bits within a reg - ister must always be written with a value of 0. the ir_ctl register is described in t able 67 . t able 66. gpio mode selection when using the irda encoder/decoder gpio port d bits allowable gpio port mode allowable port mode functions pd0 7 alternate function pd1 7 alternate function pd2C pd7 any other than gpio mode 7 (1, 2, 3, 4, 5, 6, 8, or 9) output, input, open-drain, open-source, level-sensitive interrupt input, or edge- triggered interrupt input t able 67. infrared encoder/decoder control registe r ( ir_ctl = 00bfh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:3] 000000 reserved. 2 loop_back 0 internal loop back mode is disabled. 1 internal loop back mode is enabled. ir_txd output is inverted and connected to ir_rxd input for internal loop back testing. 1 ir_rxen 0 ir_rxd data is ignored. 1 ir_rxd data is passed to uart0 r x d .
ps013012-1004 preliminary infrared encoder/decoder ez80l92 mcu product specification 126 0 ir_en 0 infrared encoder/decoder is disabled. 1 infrared encoder/decoder is enabled. bit position v alue description
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 127 serial peripheral interface the serial peripheral interface ( spi) is a synchronous interface allowing several spi-type devices to be interconnected. the spi is a full-duplex, synchronous, character -oriented communication channel that employs a four -wire interface. the spi block consists of a transmitter , receiver , baud rate generator , and control unit. during an spi transfer , data is sent and received simultaneously by both the master and the slave spi devices. in a serial peripheral interface, separate signals are required for data and clock. the spi may be configured as either a master or a slave. the connection of two spi devices (one master and one slave) and the direction of data transfer is demonstrated in figures 27 and 28 . figure 27. spi master device figure 28. spi slave device master miso dataout clkout ss bit 0 8-bit shift register baud rate generator bit 7 sck datain slave mosi miso sck dataout ss bit 0 8-bit shift register bit 7 datain enable clkin
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 128 spi signals the four basic spi signals are: ? miso (master-in, slave-out) ? mosi (master-out, slave-in) ? sck (spi serial clock) ? ss (slave select) these spi signals are discussed in the following paragraphs. each signal is described in both master and sla ve modes. master-in, slave-out the master -in, slave-out ( miso) pin is configured as an input in a master device and as an output in a slave device. it is one of the two lines that transfer serial data, with the most significant bit sent first. the miso pin of a slave device is placed in a high-impedance state if the slave is not selected. when the spi is not enabled, this signal is in a high- impedance state. master-out, slave-in the master -out, slave-in ( mosi) pin is configured as an output in a master device and as an input in a slave device. it is one of the two lines that transfer serial data, with the most significant bit sent first. when the spi is not enabled, this signal is in a high-impedance state. slave select the active low slave select ( ss ) input signal is used to select the spi as a slave device. it must be low prior to all data communication and must stay low for the duration of the data transfer . the ss input signal must be high for the spi to operate as a master device. if the ss sig - nal goes low , a mode fault error flag ( modf) is set in the spi_sr register . see the spi status register (spi_sr) on page 135 for more information. when the clock phase ( cpha) is set to 0, the shift clock is the logical or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha is set to 1, ss can remain low for several spi characters. in cases where there is only one spi slave, its ss line could be tied low as long as cpha is set to 1. see the spi control register (spi_ctl) on page 134 for more information about cpha.
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 129 serial clock the serial clock ( sck) is used to synchronize data movement both in and out of the device through its mosi and miso pins. the master and slave are each capable of exchanging a byte of data during a sequence of eight clock cycles. because sck is gener - ated by the master , the sck pin becomes an input on a slave device. the spi contains an internal divide-by-two clock divider . in master mode, the spi serial clock is one-half the frequency of the clock signal created by the spi s baud rate generator . as demonstrated in figure 29 and t able 68 , four possible timing relations may be chosen by using control bits cpol and cpha in the spi control register . see the spi control register (spi_ctl) on page 134 . both the master and slave must operate with the identi - cal timing, clock polarity (cpol), and clock polarity (cpha). the master device always places data on the mosi line a half-cycle before the clock edge (sck signal), in order for the slave device to latch the data. figure 29. spi t iming t able 68. spi clock phase a nd clock polarity o peration cpha cpol sck t ransmit edge sck receive edge sck idle state ss high between characters? 0 0 falling rising low y es 0 1 rising falling high y es sck (cpol bit = 0) sck (cpol bit = 1) sample input (cpha bit = 0) data out sample input (cpha bit = 1) data out enable (to slave) number of cycles on the sck signal 1234 5678 msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 130 spi functional description when a master transmits to a slave device via the mosi signal, the slave device responds by sending data to the master via the master's miso signal. the resulting implication is a full-duplex transmission, with both data out and data in synchronized with the same clock signal. thus the byte transmitted is replaced by the byte received and eliminates the requirement for separate transmit-empty and receive-full status bits. a single status bit, spif , is used to signify that the i/o operation is completed, see the spi status register (spi_sr) on page 135 . the spi is double-buf fered on read, but not on w rite. if a w rite is performed during data transfer , the transfer occurs uninterrupted, and the w rite is unsuccessful. this condition causes the write collision ( wcol) status bit in the spi_sr register to be set. after a data byte is shifted, the spif flag of the spi_sr register is set. in spi master mode, the sck pin is an output. it idles high or low , depending on the cpol bit in the spi_ctl register , until data is written to the shift register . data transfer is initiated by writing to the transmit shift register , spi_tsr. eight clocks are then generated to shift the eight bits of transmit data out the mosi pin while shifting in eight bits of data on the miso pin. after transfer , the sck signal idles. in spi sla ve mode, the start logic receives a logic low from the ss pin and a clock input at the sck pin, and the slave is synchronized to the master . data from the master is received serially from the slave mosi signal and loads the 8-bit shift register . after the 8- bit shift register is loaded, its data is parallel transferred to the read buf fer . during a w rite cycle data is written into the shift register , then the slave waits for the spi master to ini - tiate a data transfer , supply a clock signal, and shift the data out on the slave's miso sig - nal. if the cpha bit in the spi_ctl register is 0, a transfer begins when ss pin signal goes low and the transfer ends when ss goes high after eight clock cycles on sck. when the cpha bit is set to 1, a transfer begins the first time sck becomes active while ss is low and the transfer ends when the spif flag gets set. 1 0 rising falling low no 1 1 falling rising high no t able 68. spi clock phase a nd clock polarity o peration cpha cpol sck t ransmit edge sck receive edge sck idle state ss high between characters?
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 131 spi flags mode fault the mode fault flag ( modf ) indicates that there may be a multimaster conflict for sys - tem control. the modf bit is normally cleared to 0 and is only set to 1 when the master device s ss pin is pulled low . when a mode fault is detected, the following occurs: 1. the modf flag (spi_sr[4]) is set to 1. 2. the spi device is disabled by clearing the spi_en bit (spi_ctl[5]) to 0. 3. the master_en bit (spi_ctl[4]) is cleared to 0, forcing the device into slave mode. 4. if the spi interrupt is enabled by setting irq_en (spi_ctl[7]) high, an spi inter - rupt is generated. clearing the mode fault flag is performed by reading the spi status register . the other spi control bits ( spi_en and master_en ) must be restored to their original states by user software after the mode fault flag is cleared. w rite collision the write collision flag, wcol (spi_sr[5]), is set to 1 when an attempt is made to write to the spi t ransmit shift register (spi_tsr) while data transfer occurs. clearing the wcol bit is performed by reading spi_sr with the wcol bit set. spi baud rate generator the spi s baud rate generator creates a lower frequency clock from the high-frequency system clock. the baud rate generator output is used as the clock source by the spi. baud rate generator functional description the spi s baud rate generator consists of a 16-bit downcounter , two 8-bit registers, and associated decoding logic. the baud rate generator s initial value is defined by the two brg divisor latch registers, {spi_brg_h, spi_brg_l}. at the rising edge of each system clock, the brg decrements until it reaches the value 0001h . on the next system clock rising edge, the brg reloads the initial value from {spi_brg_h, spi_brg_l) and outputs a pulse to indicate the end-of-count. calculate the spi data rate with the follow - ing equation: spi data rate (bits/s) = system clock frequency 2 x spi baud rate generator divisor
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 132 upon reset , the 16-bit brg divisor value resets to 0002h . when the spi is operating as a master , the brg divisor value must be set to a value of 0003h or greater . when the spi is operating as a slave, the brg divisor value must be set to a value of 0004h or greater . a software w rite to either the low- or high-byte registers for the brg divisor latch causes both the low and high bytes to load into the brg counter , and causes the count to restart. data transfer procedure with spi configured as the master 1. load the spi baud rate generator registers, spi_brg_h and spi_brg_l. 2. external device must deassert the ss pin if currently asserted. 3. load the spi control register , spi_ctl. 4. assert the enable pin of the slave device using a gpio pin. 5. load the spi t ransmit shift register , spi_tsr. 6. when the spi data transfer is complete, deassert the enable pin of the slave device. data transfer procedure with spi configured as a slave 1. load the spi baud rate generator registers, spi_brg_h and spi_brg_l. 2. load the spi t ransmit shift register , spi_tsr. this load cannot occur while the spi slave is currently receiving data. 3. w ait for the external spi master device to initiate the data transfer by asserting ss . spi registers there are six registers in the serial peripheral interface which provide control, status, and data storage functions. the spi registers are described in the following paragraphs. spi baud rate generator registerslow byte and high byte these registers hold the low and high bytes of the 16-bit divisor count loaded by the pro - cessor for baud rate generation. the 16-bit clock divisor value is returned by {spi_brg_h, spi_brg_l}. upon reset , the 16-bit brg divisor value resets to 0002h . when configured as a master , the 16-bit divisor value must be between 0003h and ffffh , inclusive. when configured as a slave, the 16-bit divisor value must be between 0004h and ffffh , inclusive. a w rite to either the low or high byte registers for the brg divisor latch causes both bytes to be loaded into the brg counter and the count restarted. see t ables 69 and 70 .
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 133 t able 69. spi baud rate generator registerlow byt e ( spi_brg_l = 00b8h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 1 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] spi_brg_l 00hC ffh these bits represent the low byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {spi_brg_h, spi_brg_l}. t able 70. spi baud rate generator registerhigh byt e ( spi_brg_h = 00b9h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] spi_brg_h 00hC ffh these bits represent the high byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {spi_brg_h, spi_brg_l}.
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 134 spi control register this register is used to control and setup the serial peripheral interface. the spi should be disabled prior to making any changes to cpha or cpol. see t able 71 . t able 71. spi control registe r ( spi_ctl = 00bah) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 1 0 0 cpu access r/w r r/w r/w r/w r/w r r note: r = read only; r/w = read/write. bit position v alue description 7 irq_en 0 spi system interrupt is disabled. 1 spi system interrupt is enabled. 6 0 reserved. 5 spi_en 0 spi is disabled. 1 spi is enabled. 4 master_en 0 when enabled, the spi operates as a slave. 1 when enabled, the spi operates as a master. 3 cpol 0 master sck pin idles in a low (0) state. 1 master sck pin idles in a high (1) state. 2 cpha 0 ss must go high after transfer of every byte of data. 1 ss can remain low to transfer any number of data bytes. [1:0] 00 reserved.
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 135 spi status register the spi status read-only register returns the status of data transmitted using the serial peripheral interface. reading the spi_sr register clears bits 7, 6, and 4 to a logical 0. see t able 72 . t able 72. spi status registe r ( spi_sr = 00bbh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description 7 spif 0 spi data transfer is not finished. 1 spi data transfer is finished. if enabled, an interrupt is generated. this bit flag is cleared to 0 by a read of the spi_sr register. 6 wcol 0 an spi write collision is not detected. 1 an spi write collision is detected. this bit flag is cleared to 0 by a read of the spi_sr registers. 5 0 reserved. 4 modf 0 a mode fault ( multimaster conflict) is not detected. 1 a mode fault (multimaster conflict) is detected. this bit flag is cleared to 0 by a read of the spi_sr register. [3:0] 0000 reserved.
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 136 spi t ransmit shift register the spi t ransmit shift register (spi_tsr) is used by the spi master to transmit data onto the spi serial bus to the slave device. a w rite to the spi_tsr register places data directly into the shift register for transmission. a w rite to this register within an spi device config - ured as a master initiates transmission of the byte of the data loaded into the register . at the completion of transmitting a byte of data, the spif status bit (spi_sr[7]) is set to 1 in both the master and slave devices. the spi t ransmit shift w rite-only register shares the same address space as the spi receive buf fer read-only register . see t able 73 . t able 73. spi t ransmit shift registe r ( spi_tsr = 00bch) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] tx_data 00hC ffh spi transmit data.
ps013012-1004 preliminary serial peripheral interface ez80l92 mcu product specification 137 spi receive buffer register the spi receive buf fer register (spi_rbr) is used by the spi slave to receive data from the serial bus. the spif bit must be cleared prior to a second transfer of data from the shift register or an overrun condition exists. in cases of overrun the byte that caused the overrun is lost. the spi receive buf fer read-only register shares the same address space as the spi t ransmit shift w rite-only register . see t able 74 . t able 74. spi receive buffer registe r ( spi_rbr = 00bch) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] rx_data 00hC ffh spi received data.
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 138 i 2 c serial i/o interface i 2 c general characteristics the i 2 c serial i/o bus is a two-wire communication interface that can operate in four modes: ? master transmit ? master receive ? slave transmit ? slave receive the i 2 c interface consists of the serial clock ( scl) and the serial data ( sda). both sda and scl are bidirectional lines, connected to a positive supply voltage via an exter - nal pull-up resistor . when the bus is free, both lines are high. the output stages of devices connected to the bus must be configured as open-drain outputs. data on the i 2 c bus can be transferred at a rate of up to 100 kbps in standard mode, or up to 400 kbps in f ast mode. one clock pulse is generated for each data bit transferred. clocking overview if another device on the i 2 c bus drives the clock line when the i 2 c is in master mode, the i 2 c synchronizes its clock to the i 2 c bus clock. the high period of the clock is deter - mined by the device that generates the shortest high clock period. the low period of the clock is determined by the device that generates the longest low clock period. a slave may stretch the low period of the clock to slow down the bus master . the low period may also be stretched for handshaking purposes. this can be done after each bit transfer or each byte transfer . the i 2 c stretches the clock after each byte transfer until the iflg bit in the i2c_ctl register is cleared. bus arbitration overview in master mode, the i 2 c checks that each transmitted logic 1 appears on the i 2 c bus as a logic 1. if another device on the bus overrules and pulls the sda signal low , arbitration is lost. if arbitration is lost during the transmission of a data byte or a not-acknowledge bit, the i 2 c returns to the idle state. if arbitration is lost during the transmission of an address, the i 2 c switches to sla ve mode so that it can recognize its own slave address or the general call address.
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 139 data v alidity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low as illustrated in figure 30 . st art and st op conditions w ithin the i 2 c bus protocol, unique situations arise which are defined as st ar t and st op conditions. see figure 31 . a high-to-low transition on the sda line while scl is high indicates a st ar t condition. a low-to-high transition on the sda line while scl is high defines a st op condition. st ar t and st op conditions are always generated by the master . the bus is considered to be busy after the start condition. the bus is considered to be free a defined time after the stop condition. figure 30. i 2 c clock and data relationship figure 31. st art and st op conditions in i 2 c protocol a signal l signal data line stable data valid change of data allowed sda signal start condition stop condition scl signal sp
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 140 transferring data byte format every character transferred on the sda line must be a single 8-bit byte. the number of bytes that can be transmitted per transfer is unrestricted. each byte must be followed by an acknowledge (ack) 1 . data is transferred with the most significant bit (msb) first. see figure 32 . a receiver can hold the scl line low to force the transmitter into a wait state. data transfer then continues when the receiver is ready for another byte of data and releases scl. acknowledge data transfer with an ack function is obligatory . the ack-related clock pulse is gener - ated by the master . the transmitter releases the sda line (high) during the ack clock pulse. the receiver must pull down the sda line during the ack clock pulse so that it remains stable low during the high period of this clock pulse. see figure 33 . a receiver that is addressed is obliged to generate an ack after each byte is received. when a slave-receiver doesn't acknowledge the slave address (for example, unable to receive because it's performing some real-time function), the data line must be left high by the slave. the master then generates a st op condition to abort the transfer . if a slave-receiver acknowledges the slave address, but cannot receive any more data bytes, the master must abort the transfer . the abort is indicated by the slave generating the not acknowledge ( nack) on the first byte to follow . the slave leaves the data line high and the master generates the st op condition. if a master -receiver is involved in a transfer , it must signal the end of data to the slave- transmitter by not generating an ack on the final byte that is clocked out of the slave. the 1. ack is defined as a general acknowledge bit. by contrast, the i 2 c acknowledge bit is repre - sented as aak, bit 2 of the i 2 c control register, which identifies which ack signal to transmit. see table 84 on page 154 . figure 32. i 2 c frame structure sda signal scl signal start condition clock line held low by receiver stop condition s p acknowledge from receiver msb ack 9 1 9 12 8 acknowledge from receiver
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 141 slave-transmitter must release the data line to allow the master to generate a st op or a repeated start condition. clock synchronization all masters generate their own clocks on the scl line to transfer messages on the i 2 c bus. data is only valid during the high period of each clock. clock synchronization is performed using the wired and connection of the i 2 c interfaces to the scl line, meaning that a high-to-low transition on the scl line causes the rele - vant devices to start counting from their low period. when a device clock goes low , it holds the scl line in that state until the clock high state is reached. see figure 34 . the low-to-high transition of this clock, however , may not change the state of the scl line if another clock is still within its low period. the scl line is held low by the device with the longest low period. devices with shorter low periods enter a high wait-state during this time. when all devices concerned count of f their low period, the clock line is released and goes high. there is no dif ference between the device clocks and the state of the scl line, and all of the devices start counting their high periods. the first device to complete its high period again pulls the scl line low . in this way , a synchronized scl clock is generated with its low period determined by the device with the longest clock low period, and its high period determined by the one with the shortest clock high period. figure 33. i 2 c acknowledge data output by transmitter data output by receiver scl signal from master start condition s msb 1 clock pulse for acknowledge 9 12 8
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 142 arbitration a master may start a transfer only if the bus is free. t wo or more masters may generate a start condition within the minimum hold time of the st ar t condition which results in a defined start condition to the bus. arbitration takes place on the sda line, while the scl line is at the high level, in such a way that the master which transmits a high level, while another master is transmitting a low level switches of f its data output stage because the level on the bus doesn't correspond to its own level. arbitration can continue for many bits. its first stage is comparison of the address bits. if the masters are each trying to address the same device, arbitration continues with compar - ison of the data. because address and data information about the i 2 c bus is used for arbi - tration, no information is lost during this process. a master which loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. if a master also incorporates a slave function and it loses arbitration during the addressing stage, it's possible that the winning master is trying to address it. the losing master must switch over immediately to its slave-receiver mode. figure 34 illustrates the arbitration procedure for two masters. of course, more may be involved (depending on how many masters are connected to the bus). the moment there is a dif ference between the internal data level of the master generating da t a 1 and the actual level on the sda line, its data output is switched of f, which means that a high output level is then connected to the bus. as a result, the data transfer initiated by the winning master is not af fected. because con - trol of the i 2 c bus is decided solely on the address and data sent by competing masters, there is no central master , nor any order of priority on the bus. special attention must be paid if, during a serial transfer , the arbitration procedure is still in progress at the moment when a repeated st ar t c ondition or a st op condition is trans - mitted to the i 2 c bus. if it is possible for such a situation to occur , the masters involved must send this repeated st ar t condition or st op condition at the same position in the format frame. in other words, arbitration is not allowed between: figure 34. clock synchronization in i 2 c protocol clk1 signal clk2 signal scl signal counter reset wait state start counting high period
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 143 ? a repeated start condition and a data bit ? a stop condition and a data bit ? a repeated start condition and a stop condition clock synchronization for handshake the clock synchronizing mechanism can function as a handshake, enabling receivers to cope with fast data transfers, on either a byte or bit level. the byte level allows a device to receive a byte of data at a fast rate, but allows the device more time to store the received byte or to prepare another byte for transmission. slaves hold the scl line low after reception and acknowledge the byte, forcing the master into a wait state until the slave is ready for the next byte transfer in a handshake procedure. operating modes master t ransmit in master transmit mode, the i 2 c transmits a number of bytes to a slave receiver . enter master transmit mode by setting the st a bit in the i2c_ctl register to 1. the i 2 c then tests the i 2 c bus and transmits a st ar t condition when the bus is free. when a st ar t condition is transmitted, the iflg bit is 1 and the status code in the i2c_sr register is 08h . before this interrupt is serviced, the i2c_dr register must be loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the lsb cleared to 0 to specify transmit mode. the iflg bit should now be cleared to 0 to prompt the transfer to continue. after the 7-bit slave address (or the first part of a 10-bit address) plus the w rite bit are transmitted, the iflg is set again. a number of status codes are possible in the i2c_sr register . see t able 75 .
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 144 if 10-bit addressing is being used, then the status code is 18h or 20h after the first part of a 10-bit address plus the w rite bit are successfully transmitted. after this interrupt is serviced and the second part of the 10-bit address is transmitted, the i2c_sr register contains one of the codes in t able 76 . t able 75. i 2 c master t ransmit status codes code i 2 c state mcu response next i 2 c action 18h addr+w transmitted 1 , ack received for a 7-bit address: write byte to data, clear iflg transmit data byte, receive ack or set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit stop then start for a 10-bit address: write extended address byte to data, clear iflg transmit extended address byte 20h addr+w transmitted, ack not received same as code 18h same as code 18h 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus is free 68h arbitration lost, +w received, ack transmitted clear iflg, aak = 0 2 receive data byte, transmit nack or clear iflg, aak = 1 receive data byte, transmit ack 78h arbitration lost, general call addr received, ack transmitted same as code 68h same as code 68h b0h arbitration lost, sla+r received, ack transmitted write byte to data, clear iflg, clear aak = 0 transmit last byte, receive ack or write byte to data, clear iflg, set aak = 1 transmit data byte, receive ack notes: 1. w is defined as the w r ite bit; i.e., the lsb is cleared to 0. 2. aak is defined as the i 2 c acknowledge bit.
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 145 if a repeated st ar t condition is transmitted, the status code is 10h instead of 08h . after each data byte is transmitted, the iflg is 1 and one of the status codes listed in t able 77 is in the i2c_sr register . t able 76. i 2 c 10-bit master t ransmit status codes code i 2 c state mcu r esponse next i 2 c action 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus free 68h arbitration lost, sla+w received, ack transmitted clear iflg, clear aak = 0 receive data byte, transmit nack or clear iflg, set aak = 1 receive data byte, transmit ack b0h arbitration lost, sla+r received, ack transmitted write byte to data, clear iflg, clear aak = 0 transmit last byte, receive ack or write byte to data, clear iflg, set aak = 1 transmit data byte, receive ack d0h second address byte + w transmitted, ack received write byte to data, clear iflg transmit data byte, receive ack or set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit stop then start d8h second address byte + w transmitted, ack not received same as code d0h same as code d0h t able 77. i 2 c master t ransmit status codes for data bytes code i 2 c state mcu response next i 2 c action 28h data byte transmitted, ack received write byte to data, clear iflg transmit data byte, receive ack or set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit start then stop
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 146 when all bytes are transmitted, the processor should write a 1 to the stp bit in the i2c_ctl register . the i 2 c then transmits a st op condition, clears the stp bit and returns to the idle state. master receive in master receive mode, the i 2 c receives a number of bytes from a slave transmit - ter . after the st ar t condition is transmitted, the iflg bit is 1 and the status code 08h is loaded in the i2c_sr register . the i2c_dr register should be loaded with the slave address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a read. the iflg bit should be cleared to 0 as a prompt for the transfer to continue. when the 7-bit slave address (or the first part of a 10-bit address) and the read bit are transmitted, the iflg bit is set and one of the status codes listed in t able 78 is in the i2c_sr register . 30h data byte transmitted, ack not received same as code 28h same as code 28h 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus free t able 78. i 2 c master receive status codes code i 2 c state mcu response next i 2 c action 40h addr + r transmitted, ack received for a 7-bit address, clear iflg, aak = 0 receive data byte, transmit nack or clear iflg, aak = 1 receive data byte, transmit ack for a 10-bit address write extended address byte to data, clear iflg transmit extended address byte note: r = read bit; in essence, the lsb is set to 1. t able 77. i 2 c master t ransmit status codes for data bytes (continued) code i 2 c state mcu response next i 2 c action
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 147 if 10-bit addressing is being used, the slave is first addressed using the full 10-bit address plus the w rite bit. the master then issues a restart followed by the first part of the 10-bit address again, but with the read bit. the status code then becomes 40h or 48h . it is the responsibility of the slave to remember that it had been selected prior to the restart. if a repeated st ar t condition is received, the status code is 10h instead of 08h . after each data byte is received, the iflg is set and one of the status codes listed in t able 79 is in the i2c_sr register . 48h addr + r transmitted, ack not received for a 7-bit address: set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit stop then start for a 10-bit address: write extended address byte to data, clear iflg transmit extended address byte 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus is free 68h arbitration lost, sla+w received, ack transmitted clear iflg, clear aak = 0 receive data byte, transmit nack or clear iflg, set aak = 1 receive data byte, transmit ack 78h arbitration lost, general call addr received, ack transmitted same as code 68h same as code 68h b0h arbitration lost, sla+r received, ack transmitted write byte to data, clear iflg, clear aak = 0 transmit last byte, receive ack or write byte to data, clear iflg, set aak = 1 transmit data byte, receive ack t able 78. i 2 c master receive status codes code i 2 c state mcu response next i 2 c action note: r = read bit; in essence, the lsb is set to 1.
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 148 when all bytes are received, a nack should be sent, then the processor should write a 1 to the stp bit in the i2c_ctl register . the i 2 c then transmits a st op condition, clears the stp bit and returns to the idle state. slave t ransmit in slave transmit mode, a number of bytes are transmitted to a master receiver . the i 2 c enters slave transmit mode when it receives its own slave address and a read bit after a st ar t condition. the i 2 c then transmits an acknowledge bit (if the aak bit is set to 1) and sets the iflg bit in the i2c_ctl register and the i2c_sr register con - tains the status code a8h . when i 2 c contains a 10-bit slave address (signified by f0h?7h in the i2c_sar register), it transmits an acknowledge after the first address byte is received after a restart. an interrupt is generated, iflg is set but the status does not change. no second address byte is sent by the master . it is up to the slave to remember it had been selected prior to the restart. i 2 c goes from master mode to slave transmit mode when arbitration is lost dur - ing the transmission of an address, and the slave address and read bit are received. this action is represented by the status code b0h in the i2c_sr register . the data byte to be transmitted is loaded into the i2c_dr register and the iflg bit cleared. after the i 2 c transmits the byte and receives an acknowledge, the iflg bit is set and the i2c_sr register contains b8h . when the final byte to be transmitted is loaded into the i2c_dr register , the aak bit is cleared when the iflg is cleared. after the final byte t able 79. i 2 c master receive status codes for data bytes code i 2 c state mcu response next i 2 c action 50h data byte received, ack transmitted read data, clear iflg, clear aak = 0 receive data byte, transmit nack or read data, clear iflg, set aak = 1 receive data byte, transmit ack 58h data byte received, nack transmitted read data, set sta, clear iflg transmit repeated start or read data, set stp, clear iflg transmit stop or read data, set sta & stp, clear iflg transmit stop then start 38h arbitration lost in nack bit same as master transmit same as master transmit note:
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 149 is transmitted, the iflg is set and the i2c_sr register contains c8h a nd the i 2 c returns to the idle state. the aak bit must be set to 1 before reentering slave mode. if no acknowledge is received after transmitting a byte, the iflg is set and the i2c_sr register contains c0h . the i 2 c then returns to the idle state. if a st op condition is detected after an acknowledge bit, the i 2 c returns to the idle state. slave receive in slave receive mode, a number of data bytes are received from a master transmit - ter . the i 2 c enters slave receive mode when it receives its own slave address and a w rite bit (lsb = 0) after a st ar t condition. the i 2 c transmits an acknowledge bit and sets the iflg bit in the i2c_ctl register and the i2c_sr register contains the status code 60h . the i 2 c also enters slave receive mode when it receives the general call address 00h (if the gce bit in the i2c_sar register is set). the status code is then 70h . when the i 2 c contains a 10-bit slave address (signified by f0h?7h in the i2c_sar register), it transmits an acknowledge after the first address byte is received but no interrupt is generated. iflg is not set and the status does not change. the i 2 c generates an interrupt only after the second address byte is received. the i 2 c sets the iflg bit and loads the status code as described above. i 2 c goes from master mode to slave receive mode when arbitration is lost during the transmission of an address, and the slave address and w rite bit (or the general call address if the cge bit in the i2c_sar register is set to 1) are received. the status code in the i2c_sr register is 68h if the slave address is received or 78h if the general call address is received. the iflg bit must be cleared to 0 to allow data transfer to continue. if the aak bit in the i2c_ctl register is set to 1 then an acknowledge bit (low level on sda) is transmitted and the iflg bit is set after each byte is received. the i2c_sr regis - ter contains the status code 80h or 90h if slave receive mode is entered with the general call address. the received data byte can be read from the i2c_dr register and the iflg bit must be cleared to allow the transfer to continue. if a st op condition or a repeated st ar t condition is detected after the acknowledge bit, the iflg bit is set and the i2c_sr register contains status code a0h . if the aak bit is cleared to 0 during a transfer , the i 2 c transmits a not-acknowledge bit (high level on sda) after the next byte is received, and set the iflg bit. the i2c_sr reg - ister contains the status code 88h or 98h if slave receive mode is entered with the general call address. the i 2 c returns to the idle state when the iflg bit is cleared to 0. note:
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 150 i 2 c registers addressing the processor interface provides access to six 8-bit registers: four read/w rite registers, one read-only register and two w rite-only registers, as indicated in t able 80 . resetting the i 2 c registers hardware reset . when the i 2 c is reset by a hardware reset of the ez80l92 , the i2c_sar , i2c_xsar , i2c_dr and i2c_ctl registers are cleared to 00h ; while the i2c_sr register is set to f8h . software reset . perform a software reset by writing any value to the i 2 c software reset register ( i2c_srr ). a software reset sets the i 2 c back to idle and the stp , st a, and iflg bits of the i2c_ctl register to 0. i 2 c slave address register the i2c_sar register provides the 7-bit address of the i 2 c when in slave mode and allows 10-bit addressing in conjunction with the i2c_xsar register . i2c_sar[7:1] = sla[6:0] is the 7-bit address of the i 2 c when in 7-bit slave mode. when the i 2 c receives this address after a st ar t condition, it enters slave mode. i2c_sar[7] corresponds to the first bit received from the i 2 c bus. when the register receives an address starting with f7h to f0h (i2c_sar[7:3] = 1 1 1 10b), the i 2 c recognizes that a 10-bit slave addressing mode is being selected. the i 2 c sends an ack after receiving the i2c_sar byte (the device does not generate an interrupt at this point). after the next byte of the address (i2c_xsar) is received, the i 2 c generates an interrupt and goes into slave mode. then i2c_sar[2:1] are used as the upper 2 bits for the 10-bit extended address. the full 10-bit address is supplied by {i2c_sar[2:1], i2c_xsar[7:0]}. see t able 81 . t able 80. i 2 c register descriptions register description i2c_sar slave address register i2c_xsar extended slave address register i2c_dr data byte register i2c_ctl control register i2c_sr status register (read-only) i2c_ccr clock control register (write-only) i2c_srr software reset register (write-only)
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 151 i 2 c extended slave address register the i2c_xsar register is used in conjunction with the i2c_sar register to provide 10- bit addressing of the i 2 c when in slave mode. the i2c_sar value forms the lower 8 bits of the 10-bit slave address. the full 10-bit address is supplied by {i2c_sar[2:1], i2c_xsar[7:0]}. when the register receives an address starting with f7h to f0h (i2c_sar[7:3] = 1 1 1 10b), the i 2 c recognizes that a 10-bit slave addressing mode is being selected. the i 2 c sends an ack after receiving the i2c_xsar byte (the device does not generate an interrupt at this point). after the next byte of the address (i2c_xsar) is received, the i 2 c generates an interrupt and goes into sla ve mode. then i2c_sar[2:1] are used as the upper 2 bits for the 10-bit extended address. the full 10-bit address is supplied by {i2c_sar[2:1], i2c_xsar[7:0]}. see t able 82 . t able 81. i 2 c slave address registe r ( i2c_sar = 00c8h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:1] sla 00hC 7fh 7-bit slave address or upper 2 bits,i2c_sar[2:1], of address when operating in 10-bit mode. 0 gce 0 i 2 c not enabled to recognize the general call address. 1 i 2 c enabled to recognize the general call address. t able 82. i 2 c extended slave address registe r ( i2c_xsar = 00c9h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] slax 00hC ffh least significant 8 bits of the 10-bit extended slave address.
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 152 i 2 c data register this register contains the data byte/slave address to be transmitted or the data byte just received. in transmit mode, the most significant bit of the byte is transmitted first. in receive mode, the first bit received is placed in the most significant bit of the register . after each byte is transmitted, the i2c_dr register contains the byte that is present on the bus in case a lost arbitration event occurs. see t able 83 . i 2 c control register the i2c_ctl register is a control register that is used to control the interrupts and the master slave relationships on the i 2 c bus. when the interrupt enable bit (ien) is set to 1, the interrupt line goes high when the iflg is set to 1. when ien is cleared to 0, the interrupt line always remains low . when the bus enable bit (enab) is set to 0, the i 2 c bus inputs sclx and sdax are ignored and the i 2 c module does not respond to any address on the bus. when enab is set to 1, the i 2 c responds to calls to its slave address and to the general call address if the gce bit (i2c_sar[0]) is set to 1. when the master mode start bit ( st a) is set to 1, the i 2 c enters master mode and sends a st ar t condition on the bus when the bus is free. if the st a bit is set to 1 when the i 2 c module is already in master mode and one or more bytes are transmitted, then a repeated st ar t condition is sent. if the st a bit is set to 1 when the i 2 c block is being accessed in sla ve mode, the i 2 c completes the data transfer in sla ve mode and then enters master mode when the bus is released. the st a bit is automatically cleared after a st ar t condition is set. w riting a 0 to this bit produces no ef fect. if the master mode stop bit (stp) is set to 1 in master mode, a st op condition is transmitted on the i 2 c bus. if the stp bit is set to 1 in slave move, the i 2 c module oper - ates as if a st op condition is received, but no st op condition is transmitted. if both st a and stp bits are set, the i 2 c block first transmits the st op condition (if in master t able 83. i 2 c data registe r ( i2c_dr = 00cah) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] data 00hC ffh i 2 c data byte.
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 153 mode) and then transmit the st ar t c ondition. the stp bit is cleared automatically . w rit - ing a 0 to this bit produces no ef fect. the i 2 c interrupt flag (iflg) is set to 1 automatically when any of 30 of the possible 31 i 2 c states is entered. the only state that does not set the iflg bit is state f8h. if iflg is set to 1 and the ien bit is also set, an interrupt is generated. when iflg is set by the i 2 c , the low period of the i 2 c bus clock line is stretched and the data transfer is suspended. when a 0 is written to iflg, the interrupt is cleared and the i 2 c clock line is released. when the i 2 c acknowledge bit (aak) is set to 1, an acknowledge is sent during the acknowledge clock pulse on the i 2 c bus if: ? either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad - dress is received ? the general call address is received and the general call enable bit in i2c_sar is set to 1 ? a data byte is received while in master or slave modes when aak is cleared to 0, a nack is sent when a data byte is received in master or sla ve mode. if aak is cleared to 0 in the slave t ransmitter mode, the byte in the i2c_dr register is assumed to be the final byte. after this byte is transmitted, the i 2 c block enter states c8h , then returns to the idle state. the i 2 c module does not respond to its slave address unless aak is set. see t able 84 .
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 154 t able 84. i 2 c control register s ( i2c_ctl = 00cbh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r r note: r/w = read/write; r = read only. bit position v alue description 7 ien 0 i 2 c interrupt is disabled. 1 i 2 c interrupt is enabled. 6 enab 0 the i 2 c bus (scl/sda) is disabled and all inputs are ignored. 1 the i 2 c bus (scl/sda) is enabled. 5 sta 0 master mode start condition is sent. 1 master mode start-transmit start condition on the bus. 4 stp 0 master mode stop condition is sent. 1 master mode stop-transmit stop condition on the bus. 3 iflg 0 i 2 c interrupt flag is not set. 1 i 2 c interrupt flag is set. 2 aak 0 not acknowledge. 1 acknowledge. [1:0] 00 reserved.
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 155 i 2 c status register the i2c_sr register is a read-only register that contains a 5-bit status code in the five most significant bits: the three least significant bits are always 0. the read-only i2c_sr registers share the same i/o addresses as the w rite-only i2c_ccr registers. see t able 85 . there are 29 possible status codes, as listed in t able 86 . when the i2c_sr register con - tains the status code f8h , no relevant status information is available, no interrupt is gener - ated and the iflg bit in the i2c_ctl register is not set. all other status codes correspond to a defined state of the i 2 c . when each of these states is entered, the corresponding status code appears in this register and the iflg bit in the i2c_ctl register is set. when the iflg bit is cleared, the status code returns to f8h . t able 85. i 2 c status register s ( i2c_sr = 00cch) bit 7 6 5 4 3 2 1 0 reset 1 1 1 1 1 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:3] stat 00000C 11111 5-bit i 2 c status code. [2:0] 000 reserved. t able 86. i 2 c status codes code status 00h bus error 08h start condition transmitted 10h repeated start condition transmitted 18h address and write bit transmitted, ack received 20h address and write bit transmitted, ack not received 28h data byte transmitted in master mode, ack received 30h data byte transmitted in master mode, ack not received 38h arbitration lost in address or data byte
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 156 if an illegal condition occurs on the i 2 c bus, the bus error state is entered (status code 00h ). t o recover from this state, the stp bit in the i2c_ctl register must be set and the iflg bit cleared. the i 2 c then returns to the idle state. no st op condition is transmitted on the i 2 c bus. the stp and st a bits may be set to 1 at the same time to recover from the bus error . the i 2 c then sends a st ar t . 40h address and read bit transmitted, ack received 48h address and read bit transmitted, ack not received 50h data byte received in master mode, ack transmitted 58h data byte received in master mode, nack transmitted 60h slave address and write bit received, ack transmitted 68h arbitration lost in address as master, slave address and write bit received, ack transmitted 70h general call address received, ack transmitted 78h arbitration lost in address as master, general call address received, ack transmitted 80h data byte received after slave address received, ack transmitted 88h data byte received after slave address received, nack transmitted 90h data byte received after general call received, ack transmitted 98h data byte received after general call received, nack transmitted a0h stop or repeated start condition received in slave mode a8h slave address and read bit received, ack transmitted b0h arbitration lost in address as master, slave address and read bit received, ack transmitted b8h data byte transmitted in slave mode, ack received c0h data byte transmitted in slave mode, ack not received c8h last byte transmitted in slave mode, ack received d0h second address byte and write bit transmitted, ack received d8h second address byte and write bit transmitted, ack not received f8h no relevant status information, iflg = 0 t able 86. i 2 c status codes (continued) code status note:
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 157 i 2 c clock control register the i2c_ccr register is a w rite-only register . the seven lsbs control the frequency at which the i 2 c bus is sampled and the frequency of the i 2 c clock line ( scl) when the i 2 c is in master mode. the w rite-only i2c_ccr registers share the same i/o addresses as the read-only i2c_sr registers. see t able 87 . the i 2 c clocks are derived from the ez80l92 s system clock. the frequency of the ez80l92 system clock is f sck . the i 2 c bus is sampled by the i 2 c block at the frequency f samp supplied by: in master mode, the i 2 c clock output frequency on scl ( f scl ) is supplied by: the use of two separately-programmable dividers allows the master mode output fre - quency to be set independently of the frequency at which the i 2 c bus is sampled. this fea - ture is particularly useful in multimaster systems because the frequency at which the i 2 c bus is sampled must be at least 10 times the frequency of the fastest master on the bus to ensure that st ar t and st op conditions are always detected. by using two programma - t able 87. i 2 c clock control register s ( i2c_ccr = 00cch) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = read only. bit position v alue description 7 0 reserved. [6:3] m 0000C 1111 i 2 c clock divider scalar value. [2:0] n 000C 111 i 2 c clock divider exponent. f samp = f sclk 2 n f scl = f sclk 10 ? (m + 1)(2) n
ps013012-1004 preliminary i 2 c serial i/o interface ez80l92 mcu product specification 158 ble clock divider stages, a high sampling frequency can be ensured while allowing the master mode output to be set to a lower frequency . bus clock speed the i 2 c bus is defined for bus clock speeds up to 100 kbps (400 kbps in f ast mode). t o ensure correct detection of st ar t and st op conditions on the bus, the i 2 c must sam - ple the i 2 c bus at least ten times faster than the bus clock speed of the fastest master on the bus. the sampling frequency should therefore be at least 1 mhz (4 mhz in f ast mode) to guarantee correct operation with other bus masters. the i 2 c sampling frequency is determined by the frequency of the ez80l92 system clock and the value in the i2c_ccr bits 2 to 0. the bus clock speed generated by the i 2 c in master mode is determined by the frequency of the input clock and the values in i2c_ccr[2:0] and i2c_ccr[6:3]. i 2 c software reset register the i2c_srr register is a w rite-only register . w riting any value to this register performs a software reset of the i 2 c module. see t able 88 . t able 88. i 2 c software reset registe r ( i2c_srr = 00cdh) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write-only. bit position v alue description [7:0] srr 00hC ffh writing any value to this register performs a software reset of the i 2 c module.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 159 zilog debug interface introduction the zilog debug interface (zdi) provides a built-in debugging interface to the ez80 ? cpu . zdi provides basic in-circuit emulation features including: ? examining and modifying internal registers ? examining and modifying memory ? starting and stopping the user program ? setting program and data break points ? single-stepping the user program ? executing user-supplied instructions ? debugging the final product with the inclusion of one small connector ? downloading code into sram ? c source-level debugging using zilog developer studio ( zds ii ) the above features are built into the silicon. control is provided via a two-wire interface that is connected to the zp ak ii emulator . figure 35 illustrates a typical setup using a a tar get board, zp ak ii , and the host pc running zilog developer studio. refer to the zilog website for more information about zp ak ii and zds ii . zdi allows reading and writing of most internal registers without disturbing the state of the machine. reads a nd w rites to memory may occur as fast as the zdi can download and figure 35. t ypical zdi debug setup zilog developer studio zpak emulator ez80 product ta rget board c o n n e c t o r
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 160 upload data, with a maximum frequency of one-half the ez80l92 system clock frequency . t able 89 lists the recommended frequencies of the zdi clock in relation to the system clock. zdi-supported protocol zdi supports a bidirectional serial protocol. the protocol defines any device that sends data as the tr ansmitter and any receiving device as the r eceiver . the device controlling the transfer is the master and the device being controlled is the slave . the master always ini - tiates the data transfers and provides the clock for both receive and transmit operations. the zdi block on the ez80l92 is considered a slave in all data transfers. figure 36 illustrates the schematic for building a connector on a tar get board. this connec - tor allows the user to connect directly to the zp ak emulator using a six-pin header . t able 89. recommended zdi clock vs. system clock frequency system clock frequency zdi clock frequency 3C10 mhz 1 mhz 8C16 mhz 2 mhz 12C24 mhz 4 mhz 20C50 mhz 8 mhz figure 36. schematic for building a t arget board zp ak connector 6-pin target connector 1 3 5 2 4 6 ez80l92 mcu 10 k? 10 k? tck (zcl) tdi (zda) tv dd (target v ) dd
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 161 zdi clock and data conventions the two pins used for communication with the zdi block are the zdi clock pin ( zcl) and the zdi data pin ( zda). on the ez80l92 , the zcl pin is shared with the tck pin while the zda pin is shared with the tdi pin. the zcl and zda pin functions are only available when the on-chip instrumentation is disabled and the zdi is therefore enabled. for general data communication, the data value on the zda pin can change only when zcl is low (0). the only exception is the zdi st ar t bit, which is indicated by a high- to-low transition (falling edge) on the zda pin while zcl is high. data is shifted into and out of zdi, with the most significant bit (bit 7) of each byte being first in time, and the least significant bit (bit 0) last in time. all information is passed between the master and the slave in 8-bit (single-byte) units. each byte is transferred with nine clock cycles: eight to shift the data, and the ninth for internal operations. zdi start condition all zdi commands are preceded by the zdi st ar t signal, which is a high-to-low tran - sition of zda when zcl is high. the zdi slave on the ez80l92 continually monitors the zda and zcl lines for the st ar t signal and does not respond to any command until this condition is met. the master pulls zda low , with zcl high, to indicate the beginning of a data transfer with the zdi block. figures 37 and 38 illustrate a valid zdi st ar t signal prior to writing and reading data, respectively . a low-to-high transition of zda while the zcl is high produces no ef fect. data is shifted in during a w rite to the zdi block on the rising edge of zcl, as illustrated in figure 37 . data is shifted out during a read from the zdi block on the falling edge of zcl as illustrated in figure 38 . when an operation is completed, the master stops during the ninth cycle and holds the zcl signal high. figure 37. zdi w rite t iming zdi data in (write) zdi data in (write) start signal zcl zda
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 162 zdi single-bit byte separator following each 8-bit zdi data transfer , a single-bit byte separator is used. t o initiate a new zdi command, the single-bit byte separator must be high (logical 1) to allow for a new zdi st ar t command to be sent. for all other cases, the single-bit byte separator can be either low (logical 0) or high (logical 1). when zdi is configured to allow the cpu to accept external bus requests, the single-bit byte separator should be low (logical 0) during all zdi commands. this low value indicates that zdi is still operating and is not ready to relinquish the bus. the cpu does not accept the external bus requests until the single-bit byte separator is a high (logical 1). for more information about accepting bus requests in zdi debug mode, please see the bus requests during zdi debug mode section on page 166 . zdi register addressing following a st ar t signal the zdi master must output the zdi register address. all data transfers with the zdi block use special zdi registers. the zdi control registers that reside in the zdi register address space should not be confused with the ez80l92 periph - eral registers that reside in the i/o address space. many locations in the zdi control register address space are shared by two registers, one for read-only access and one for w rite-only access. as an example, a read from zdi register address 00h returns the ez80 ? product id low byte while a w rite to this same location, 00h , stores the low byte of one of the address match values used for generating break points. the format for a zdi address is seven bits of address, followed by one bit for read or w r ite control, and completed by a single-bit byte separator . the zdi executes a read or w rite operation depending on the state of the r/ w bit (0 = w rite, 1 = read). if no new figure 38. zdi read t iming zdi data out (read) zdi data out (read) start signal zcl zda
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 163 st ar t command is issued at completion of the read or w rite operation, the operation can be repeated. this allows repeated read or w rite operations without having to resend the zdi command. a st ar t signal must follow to initiate a new zdi command. figure 39 illustrates the timing for address w rites to zdi registers. zdi write operations zdi single-byte w rite for single-byte w rite operations, the address and write control bit are first written to the zdi block. following the single-bit byte separator , the data is shifted into the zdi block on the next 8 rising edges of zcl. the master terminates activity after 8 clock cycles. figure 40 illustrates the timing for zdi single-byte w rite operations. figure 39. zdi address w rite t iming figure 40. zdi single-byte data w rite t iming zdi address byte single-bit byte separator or new zdi start signal start signal 0 = write 1 = read lsb msb zcl s 1 2 3 456789 a6 a5 a4 a3 a2 a1 a0 r/w 0/1 zda zdi data byte lsb of zdi address single-bit byte separator lsb of data msb of data end of data or new zdi start signal zcl 7 8 9 1 2 3 456789 a0 write 0/1 d7 d6 d5 d4 d3 d2 d1 d0 1 zda
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 164 zdi block w rite the bl ock w r ite operation is initiated in the same manner as the single-byte w rite opera - tion, but instead of terminating the w rite operation after the first data byte is transferred, the zdi master can continue to transmit additional bytes of data to the zdi slave on the ez80l92 . after the receipt of each byte of data the zdi register address increments by 1. if the zdi register address reaches the end of the w rite-only zdi register address space ( 30h ), the address stops incrementing. figure 41 illustrates the timing for zdi block w rite operations. zdi read operations zdi single-byte read single-byte read operations are initiated in the same manner as single-byte w rite opera - tions, with the exception that the r/ w bit of the zdi register address is set to 1. upon receipt of a slave address with the r/ w bit set to 1, the ez80l92 s zdi block loads the selected data into the shifter at the beginning of the first cycle following the single-bit data separator . the most significant bit (msb) is shifted out first. figure 42 illustrates the timing for zdi single-byte read operations. figure 41. zdi block data w rite t iming zdi data bytes lsb of zdi address single-bit byte separator msb of data byte 2 msb of data byte 1 lsb of data byte 1 single-bit byte separator zcl 7 8 9 1 2 3 789129 a0 write 0/1 d7 d6 d5 d1 d0 0/1 d7 d6 1 zda
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 165 zdi block read a block read operation is initiated the same as a single-byte read; however , the zdi master continues to clock in the next byte from the zdi slave as the zdi slave continues to output data. the zdi register address counter increments with each read. if the zdi regis - ter address reaches the end of the read-only zdi register address space ( 20h ), the address stops incrementing. figure 43 illustrates the zdi s bl ock re ad timing. operation of the ez80l92 during zdi break points if the zdi forces the cpu to break, only the cpu suspends operation. the system clock continues to operate and drive other peripherals. those peripherals that can operate auton - omously from the cpu may continue to operate, if so enabled. for example, the w atch- dog t imer and programmable reload t imers continue to count during a zdi break point. figure 42. zdi single-byte data read t iming figure 43. zdi block data read t iming zdi data byte lsb of zdi address single-bit byte separator lsb of data msb of data end of data or new zdi start signal zcl 7 8 9 1 2 3 456789 a0 read 0/1 d7 d6 d5 d4 d3 d2 d1 d0 1 zda zdi data bytes lsb of zdi address single-bit byte separator msb of data byte 2 msb of data byte 1 lsb of data byte 1 single-bit byte separator zcl 7 8 9 1 2 3 789129 a0 read 0/1 d7 d6 d5 d1 d0 0/1 d7 d6 1 zda
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 166 when using the zdi interface, any w rite or read operations of peripheral registers in the i/o address space produces the same ef fect as read or w rite operations using the cpu. because many register read/w rite operations exhibit secondary ef fects, such as clearing flags or causing operations to commence, the ef fects of the read/w rite operations during a zdi break must be taken into consideration. bus requests during zdi debug mode the zdi block on the ez80l92 allows an external device to take control of the address and data bus while the ez80l92 is in debug mode. zdi_busack_en causes zdi to allow or prevent acknowledgement of bus requests by external peripherals. the bus acknowledge only occurs at the end of the current zdi operation (indicated by a high dur - ing the single-bit byte separator). the default reset condition is for bus acknowledgement to be disabled. t o allow bus acknowledgement, the zdi_busack_en must be written. when an external bus request ( busreq pin asserted) is detected, zdi waits until comple - tion of the current operation before responding. zdi acknowledges the bus request by asserting the bus acknowledge ( busack ) signal. if the zdi block is not currently shift - ing data, it acknowledges the bus request immediately . zdi uses the single-bit byte sepa - rator of each data word to determine if it is at the end of a zdi operation. if the bit is a logical 0, zdi does not assert busack to allow additional data read or w rite operations. if the bit is a logical 1, indicating completion of the zdi commands, busack is asserted. potential hazards of enabling bus requests during debug mode there are some potential hazards that the user must be aware of when enabling external bus requests during zdi debug mode. first, when the address and data bus are being used by an external source, zdi must only access zdi registers and internal cpu registers to prevent possible bus contention. the bus acknowledge status is reported in the zdi_bus_st a t register . the busack output pin also indicates the bus acknowledge state. a second hazard is that when a bus acknowledge is granted, the zdi is subject to any w ait states that are assigned to the device currently being accessed by the external peripheral. t o prevent data errors, zdi should avoid data transmission while another device is controlling the bus. finally , exiting zdi debug mode while an external peripheral controls the address and data buses, as indicated by busack assertion, may produce unpredictable results.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 167 zdi write-only registers t able 90 lists the zdi w rite-only registers. many of the zdi w rite-only addresses are shared with zdi read-only registers. t able 90. zdi w rite-only registers zdi address zdi register name zdi register function reset v alue 00h zdi_addr0_l address match 0 low byte xxh 01h zdi_addr0_h address match 0 high byte xxh 02h zdi_addr0_u address match 0 upper byte xxh 04h zdi_addr1_l address match 1 low byte xxh 05h zdi_addr1_h address match 1 high byte xxh 06h zdi_addr1_u address match 1 upper byte xxh 08h zdi_addr2_l address match 2 low byte xxh 09h zdi_addr2_h address match 2 high byte xxh 0ah zdi_addr2_u address match 2 upper byte xxh 0ch zdi_addr3_l address match 3 low byte xxh 0dh zdi_addr3_h address match 3 high byte xxh 0eh zdi_addr3_u address match 4 upper byte xxh 10h zdi_brk_ctl break c ontrol register 00h 11h zdi_master_ctl master control register 00h 13h zdi_wr_data_l write data low byte xxh 14h zdi_wr_data_h write data high byte xxh 15h zdi_wr_data_u write data upper byte xxh 16h zdi_rw_ctl read/write control register 00h 17h zdi_bus_ctl bus control register 00h 21h zdi_is4 instruction store 4 xxh 22h zdi_is3 instruction store 3 xxh 23h zdi_is2 instruction store 2 xxh 24h zdi_is1 instruction store 1 xxh 25h zdi_is0 instruction store 0 xxh 30h zdi_wr_mem write memory register xxh
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 168 zdi read-only registers t able 91 lists the zdi read-only registers. many of the zdi read-only addresses are shared with zdi w rite-only registers. zdi register definitions zdi address match registers the four sets of address match registers are used for setting the addresses for generating break points. when the accompanying brk_addr x bit is set in the zdi break control register to enable the particular address match, the current ez80l92 address is compared with the 3-byte address set, {zdi_addrx_u, zdi_addrx_h, zdi_addr_x_l}. if the cpu is operating in adl mode, the address is supplied by addr[23:0]. if the cpu is operating in z80 mode, the address is supplied by {mbase[7:0], addr[15:0]}. if a match is found, zdi issues a break to the ez80l92 placing the processor in zdi mode pending further instructions from the zdi interface block. if the address is not the first op- code fetch, the zdi break is executed at the end of the instruction in which it is exe - cuted. there are four sets of address match registers. they can be used in conjunction with each other to break on branching instructions. see t able 92 . t able 91. zdi read-only registers zdi address zdi register name zdi register function reset v alue 00h zdi_id_l ez80 ? product id low byte register 06h 01h zdi_id_h ez80 ? product id high byte register 00h 02h zdi_id_rev ez80 ? product id revision register xxh 03h zdi_stat status register 00h 10h zdi_rd_l read memory address low byte register xxh 1 1h zdi_rd_h read memory address high byte register xxh 12h zdi_rd_u read memory address upper byte register xxh 17h zdi_bus_stat bus status register 00h 20h zdi_rd_mem read memory data value xxh
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 169 zdi break control register the zdi break control register is used to enable break points. zdi asserts a break when the cpu instruction address, addr[23:0], matches the value in the zdi address match 3 registers, {zdi_addr3_u, zdi_addr3_h, zdi_addr3_l}. breaks can only occur on an instruction boundary. if the instruction address is not the beginning of an instruction (that is, for multibyte instructions), then the break occurs at the end of the current instruction. the brk_next bit is set to 1. the brk_next bit must be reset to 0 to release the break. see t able 93 . t able 92. zdi address match register s z di_addr0_l = 00h, zdi_addr0_h = 01h, zdi_addr0_u = 02h , z di_addr1_l = 04h, zdi_addr1_h = 05h, zdi_addr1_u = 06h , z di_addr2_l = 08h, zdi_addr2_h = 09h, zdi_addr2_u = 0ah , z di_addr3_l = 0ch, zdi_addr3_h = 0dh, and zdi_addr3_u = 0eh in the zdi register w rite-only address space bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write-only. bit position v alue description [7:0] zdi_addr x _l, zdi_addr x _h, or zdi_addr x _u 00hC ffh the four sets of zdi address match registers are used for setting the addresses for generating break points. the 24- bit addresses are supplied by {zdi_addrx_u, zdi_addrx_h, zdi_addrx_l, where x is 0, 1, 2, or 3.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 170 t able 93. zdi break c ontrol registe r ( zdi_brk_ctl = 10h in the zdi w rite-only register address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write-only. bit position v alue description 7 brk_next 0 the zdi break on the next cpu instruction is disabled. clearing this bit releases the cpu from its current break condition. 1 the zdi break on the next cpu instruction is enabled. the cpu can use multibyte op codes and multibyte operands. break points o nly occur on the first op code in a multibyte op code instruction. if the zcl pin is high and the zda pin is low at the end of reset, this bit is set to 1 and a break occurs on the first instruction following the reset. this bit is set automatically during zdi break on address match. a break can also be forced by writing a 1 to this bit. 6 brk_addr3 0 the zdi break, upon matching break address 3 , is disabled. 1 the zdi break, upon matching break address 3 , is enabled. 5 brk_addr2 0 the zdi break, upon matching break address 2 , is disabled. 1 the zdi break, upon matching break address 2 , is enabled. 4 brk_addr1 0 the zdi break, upon matching break address 1 , is disabled. 1 the zdi break, upon matching break address 1 , is enabled. 3 brk_addr0 0 the zdi break, upon matching break address 0 , is disabled. 1 the zdi break, upon matching break address 0 , is enabled.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 171 2 ign_low_1 0 the ignore the low byte function of the zdi address match 1 registers is disabled. if brk_addr1 is set to 1, zdi initiates a break when the entire 24-bit address, addr[23:0], matches the 3-byte value {zdi_addr1_u, zdi_addr1_h, zdi_addr1_l}. 1 the ignore the low byte function of the zdi address match 1 registers is enabled. if brk_addr1 is set to 1, zdi initiates a break when only the upper 2 bytes of the 24-bit address, addr[23:8], match the 2-byte value {zdi_addr1_u, zdi_addr1_h}. as a result, a break can occur anywhere within a 256-byte page. 1 ign_low_0 0 the ignore the low byte function of the zdi address match 1 registers is disabled. if brk_addr0 is set to 1, zdi initiates a break when the entire 24-bit address, addr[23:0], matches the 3-byte value {zdi_addr0_u, zdi_addr0_h, zdi_addr0_l}. 1 the ignore the low byte function of the zdi address match 1 registers is enabled. if the brk_addr1 is set to 0, zdi initiates a break when only the upper 2 bytes of the 24-bit address, addr[23:8], match the 2 bytes value {zdi_addr0_u, zdi_addr0_h}. as a result, a break can occur anywhere within a 256-byte page. 0 single_step 0 zdi single step mode is disabled. 1 zdi single step mode is enabled. zdi asserts a break following execution of each instruction. bit position v alue description
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 172 zdi master control register the zdi master control register provides control of the ez80l92 . it is capable of forcing a reset and waking up the ez80l92 from the low-power modes ( hal t or sleep). see t able 94 . t able 94. zdi master control registe r ( zdi_master_ctl = 1 1h in zdi register w rite address spaces) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write-only. bit position v alue description 7 zdi_reset 0 no action. 1 initiate a reset of the ez80l92 . this bit is automatically cleared at the end of the reset event. [6:0] 0000000 reserved.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 173 zdi w rite data registers these three registers are used in the zdi w rite-only register address space to store the data that is written when a w rite instruction is sent to the zdi read/w rite control register (zdi_r w_ctl). the zdi read/w rite control register is located at zdi address 16h immediately following the zdi w rite data registers. as a result, the zdi master is allowed to write the data to {zdi_wr_u, zdi_wr_h, zdi_wr_l} and the w rite com - mand in one data transfer operation. see t able 95 . t able 95. zdi w rite data register s ( zdi_wr_u = 13h, zdi_wr_h = 14h, and zdi_wr_l = 15 h i n the zdi register w rite-only address space) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write. bit position v alue description [7:0] zdi_wr_l, zdi_wr_h, or zdi_wr_l 00hC ffh these registers contain the data that is written during execution of a write operation defined by the zdi_rw_ctl register. the 24-bit data value is stored as {zdi_wr_u, zdi_wr_h, zdi_wr_l}. if less than 24 bits of data are required to complete the required operation, the data is taken from the least significant byte(s).
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 174 zdi read/w rite control register the zdi read/w rite control register is used in the zdi w rite-only register address to read data from, write data to, and manipulate the cpu s registers or memory locations. when this register is written, the ez80l92 immediately performs the operation corre - sponding to the data value written as described in t able 96 . when a read operation is exe - cuted via this register , the requested data values are placed in the zdi read data registers {zdi_rd_u, zdi_rd_h, zdi_rd_l}. when a w rite operation is executed via this reg - ister , the w rite data is taken from the zdi w rite data registers {zdi_wr_u, zdi_wr_h, zdi_wr_l}. see t able 96 . refer to the ez80 cpu user manual (um0077) for information regarding the cpu registers. t able 96. zdi read/w rite control register function s ( zdi_r w_ctl = 16h in the zdi register w rite-only address space) hex v alue command hex v alue command 00 read {mbase, a, f} zdi_rd_u mbase zdi_rd_h f zdi_rd_l a 80 write {mbase, a, f} mbase zdi_wr_u f zdi_wr_h a zdi_wr_l 01 read bc zdi_rd_u bcu zdi_rd_h b zdi_rd_l c 81 write bc bcu zdi_wr_u b zdi_wr_h c zdi_wr_l 02 read de zdi_rd_u deu zdi_rd_h d zdi_rd_l e 82 write de deu zdi_wr_u d zdi_wr_h e zdi_wr_l 03 read hl zdi_rd_u hlu zdi_rd_h h zdi_rd_l l 83 write hl hlu zdi_wr_u h zdi_wr_h l zdi_wr_l 04 read ix zdi_rd_u ixu zdi_rd_h ixh zdi_rd_l ixl 84 write ix ixu zdi_wr_u ixh zdi_wr_h ixl zdi_wr_l 05 read iy zdi_rd_u iyu zdi_rd_h iyh zdi_rd_l iyl 85 write iy iyu zdi_wr_u iyh zdi_wr_h iyl zdi_wr_l note: the ez80 ? cpu s alternate register set (a, f, b, c, d, e, hl) cannot be read directly. the zdi programmer must execute the exchange instruction (exx) to gain access to the alternate ez80 ? cpu register set.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 175 06 read sp in adl mode, sp = spl. in z80 mode, sp = sps. 86 write sp in adl mode, sp = spl. in z80 mode, sp = sps. 07 read pc zdi_rd_u pc[23:16] zdi_rd_h pc[15:8] zdi_rd_l pc[7:0] 87 write pc pc[23:16] zdi_wr_u pc[15:8] zdi_wr_h pc[7:0] zdi_wr_l 08 set adl adl 1 88 reserved 09 reset adl adl 0 89 reserved 0a exchange cpu register sets af af bc bc de de hl hl 8a reserved 0b read memory from current pc value, increment pc 8b write memory from current pc value, increment pc t able 96. zdi read/w rite control register function s ( zdi_r w_ctl = 16h in the zdi register w rite-only address space) (continued) hex v alue command hex v alue command note: the ez80 ? cpu s alternate register set (a, f, b, c, d, e, hl) cannot be read directly. the zdi programmer must execute the exchange instruction (exx) to gain access to the alternate ez80 ? cpu register set.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 176 zdi bus control register the zdi bus control register controls bus requests during debug mode. it enables or disables bus acknowledge in zdi debug mode and allows zdi to force assertion of the busack signal. this register should only be written during zdi debug mode (that is, following a break). see t able 97 . t able 97. zdi bus control registe r ( zdi_bus_ctl = 17h in the zdi register w rite- only address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write-only. bit position v alue description 7 zdi_busak_en 0 bus requests by external peripherals using the busreq pin are ignored. the bus acknowledge signal, busack , is not asserted in response to any bus requests. 1 bus requests by external peripherals using the busreq pin are accepted. a bus acknowledge occurs at the end of the current zdi operation. the bus acknowledge is indicated by asserting the busack pin in response to a bus request. 6 zdi_busak 0 deassert the bus acknowledge pin ( busack ) to return control of the address and data buses back to zdi. 1 assert the bus acknowledge pin ( busack ) to pass control of the address and data buses to an external peripheral. [5:0] 000000 reserved.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 177 instruction store 4:0 registers the zdi instruction store registers are located in the zdi register w rite-only address space. they can be written with instruction data for direct execution by the cpu. when the zdi_is0 register is written, the ez80l92 exits the zdi break state and executes a single instruction. the op codes and operands for the instruction come from these instruction store registers. the instruction store register 0 is the first byte fetched, fol - lowed by instruction store registers 1, 2, 3, and 4, as necessary . only the bytes the proces - sor requires to execute the instruction must be stored in these registers. some ez80 ? instructions, when combined with the memory mode suf fixes (.sis, .sil, .lis, or .lil), require 6 bytes to operate. these 6-byte instructions cannot be executed directly using the zdi instruction store registers. see t able 98 . the instruction store 0 register is located at a higher zdi address than the other instruction store registers. this feature allows the use of the zdi auto-address increment function to load and execute a multibyte instruction with a single data stream from the zdi master . execution of the instruction commences with writing the final byte to zdi_is0. t able 98. instruction store 4:0 register s ( zdi_is4 = 21h, zdi_is3 = 22h, zdi_is2 = 23h, zdi_is1 = 24h, and zdi_is0 = 25 h i n the zdi register w rite-only address space) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write. bit position v alue description [7:0] zdi_is4, zdi_is3, zdi_is2, zdi_is1, or zdi_is0 00hC ffh these registers contain the op codes and operands for immediate execution by the cpu following a write to zdi_is0. the zdi_is0 register contains the first op code of the instruction. the remaining zdi_isx registers contain any additional op codes or operand dates required for execution of the required instruction. note:
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 178 zdi w rite memory register a w rite to the zdi w rite memory register causes the ez80l92 to write the 8-bit data to the memory location specified by the current address in the program counter . in z80 memory mode, this address is {mbase, pc[15:0]}. in adl memory mode, this address is pc[23:0]. the program counter , pc, increments after each data w rite. however , the zdi register address does not increment automatically when this register is accessed. as a result, the zdi master is allowed to write any number of data bytes by writing to this address one time followed by any number of data bytes. see t able 99 . t able 99. zdi w rite memory registe r ( zdi_wr_mem = 30h in the zdi register w rite- only address space) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write. bit position v alue description [7:0] zdi_wr_mem 00hC ffh the 8-bit data that is transferred to the zdi slave following a write to this address is written to the address indicated by the current program counter. the program counter is incremented following each 8 bits of data. in z80 memory mode, ({mbase, pc[15:0]}) 8 bits of transferred data. in adl memory mode, (pc[23:0]) 8 bits of transferred data.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 179 ez80 ? product id low and high byte registers the ez80 ? product id low and high byte registers combine to provide a means for an external device to determine the particular ez80 ? product being addressed. for the ez80l92 , these two bytes, {zdi_id_h, zdi_id_l} return the value { 00h , 06h }. see t ables 100 and 101 . t able 100. ez80 ? product id low byte registe r ( zdi_id_l = 00h in the zdi register read-only address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 1 1 0 cpu access r r r r r r r r note: r = read-only. bit position v alue description [7:0] zdi_id_l 06h {zdi_id_h, zdi_id_l} = {00h, 06h} indicates the ez80l92 product. t able 101. ez80 ? product id high byte registe r ( zdi_id_h = 01h in the zdi register read-only address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read-only. bit position v alue description [7:0] zdi_id_h 00h {zdi_id_h, zdi_id_l} = {00h, 06h} indicates the ez80l92 product.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 180 ez80 ? product id revision register the ez80 ? product id revision register identifies the current revision of the ez80l92 product. see t able 102 . zdi status register the zdi status register provides current information about the ez80l92 and the ez80 ? cpu . see t able 103 . t able 102. ez80 ? product id revision registe r ( zdi_id_rev = 02h in the zdi register read-only address space) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: x = undetermined; r = read-only. bit position v alue description [7:0] zdi_id_rev 00hC ffh identifies the current revision of the ez80l92 product. t able 103. zdi status registe r ( zdi_st a t = 03h in the zdi register read-only address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read-only. bit position v alue description 7 zdi_active 0 the cpu is not functioning in zdi mode. 1 the cpu is currently functioning in zdi mode. 6 0 reserved. 5 halt_slp 0 ez80l92 is not currently in halt or sleep mode. 1 ez80l92 is currently in halt or sleep mode.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 181 zdi read registerslow , high, and upper the zdi register read-only address space of fers low , high, and upper functions, which contain the value read by a read operation from the zdi read/w rite control register (zdi_r w_ctl). this data is valid only while in zdi break mode and only if the instruction is read by a request from the zdi read/w rite control register . see t able 104 . 4 adl 0 the cpu is operating in z80 memory mode. (adl bit = 0). 1 the cpu is operating in adl memory mode. (adl bit = 1). 3 madl 0 the cpus mixed-memory mode (madl) bit is reset to 0. 1 the cpus mixed-memory mode (madl) bit is set to 1. 2 ief1 0 the cpus interrupt enable flag 1 is reset to 0. maskable interrupts are disabled. 1 the cpus interrupt enable flag 1 is set to 1. maskable interrupts are enabled. [1:0] reserved 00 reserved. t able 104. zdi read registerslow , high and uppe r ( zdi_rd_l = 10h, zdi_rd_h = 1 1h, and zdi_rd_u = 12 h i n the zdi register read-only address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read-only. bit position v alue description [7:0] zdi_rd_l, zdi_rd_h, or zdi_rd_u 00hC ffh values read from the memory location as requested by the zdi read control register during a zdi read operation. the 24-bit value is supplied by {zdi_rd_u, zdi_rd_h, zdi_rd_l}. bit position v alue description
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 182 zdi bus status register the zdi bus status register monitors busacks during debug mode. see t able 105 . t able 105. zdi bus control registe r ( zdi_bus_st a t = 17h in the zdi register read-only address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read-only. bit position v alue description 7 zdi_busack_en 0 bus requests by external peripherals using the busreq pin are ignored. the bus acknowledge signal, busack , is not asserted. 1 bus requests by external peripherals using the busreq pin are accepted. a bus acknowledge occurs at the end of the current zdi operation. the bus acknowledge is indicated by asserting the busack pin. 6 zdi_bus_stat 0 address and data buses are not relinquished to an external peripheral. bus acknowledge is deasserted ( busack pin is high). 1 address and data buses are relinquished to an external peripheral. bus acknowledge is asserted ( busack pin is low). [5:0] 000000 reserved.
ps013012-1004 preliminary zilog debug interface ez80l92 mcu product specification 183 zdi read memory register when a read is executed from the zdi read memory register , the ez80l92 fetches the data from the memory address currently pointed to by the program counter , pc; the pro - gram counter is then incremented. in z80 memory mode, the memory address is {mbase, pc[15:0]}. in adl memory mode, the memory address is pc[23:0]. refer to the ez80 cpu user manual (um0077) for more information regarding z80 and adl memor y modes. the program counter , pc, increments after each data read. however , the zdi register address does not increment automatically when this register is accessed. as a result, the zdi master can read any number of data bytes out of memory through the zdi read memory register . see t able 106 . t able 106. zdi read memory registe r ( zdi_rd_mem = 20h in the zdi register read-only address space) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read-only. bit position v alue description [7:0] zdi_rd_mem 00hC ffh 8-bit data read from the memory address indicated by the cpus program counter. in z80 memory mode, 8-bit data is transferred out from address {mbase, pc[15:0]}. in adl memory mode, 8-bit data is transferred out from address pc[23:0].
ps013012-1004 preliminary on-chip instrumentation ez80l92 mcu product specification 184 on-chip instrumentation introduction to on-chip instrumentation on-chip instrumentation 1 (oci?) for the zilog ez80 ? cpu core enables powerful debugging features. the oci provides run control, memory and register visibility , com - plex breakpoints, and trace history features. the oci employs all of the functions of the zilog debug interface (zdi) as described in the zdi section. it also adds the following debug features: ? control via a 4-pin jtag port that conforms to ieee standard 1149.1 (test access port and boundary-scan architecture) 2 ? complex break-point trigger functions ? break-point enhancements, such as the ability to: C define two break-point addresses that form a range C break on masked data values C start or stop trace C assert a trigger output signal ? trace history buffer ? software break-point instruction there are four sections to the oci: 1. jt ag interface 2. zdi debug control 3. t race buf fer memory 4. complex triggers oci activation oci features clock initialization circuitry so that external debug hardware can be detected during power up. the external debugger must drive the oci clock pin (tck) low at least two system clock cycles prior to the end of the reset to activate the oci block. if tck is high at the end of the reset , the oci block shuts down so that it does not draw power in normal product operation. when the oci is shut down, zdi is enabled directly and can be accessed through the clock (tck) and data (tdi) pins. see the zilog debug interface section on page 159 for more information about zdi. 1. on-chip instrumentation and oci are trademarks of first silicon solutions, inc. 2. the ez80l92 mcu d oes not contain the boundary scan register required for 1149.1 compliance.
ps013012-1004 preliminary on-chip instrumentation ez80l92 mcu product specification 185 oci interface there are five dedicated pins on the ez80l92 for the oci interface. four (tck, tms, tdi, and tdo) are required for ieee standard 1 149.1-compatible jt ag ports. the tri - gout pin provides additional testability features. these five oci pins are described in t able 107 . t able 107. oci pins symbol name t ype description tck clock. input asynchronous to the primary ez80l92 system clock. the tck period but must be at least twice the system clock period. during reset, this pin is sampled to select either oci or zdi debug modes. if low during reset, the oci is enabled. if high during reset, the oci is powered down and zdi debug mode is enabled. when zdi debug mode is active, this pin is the zdi clock. on-chip pull-up ensures a default value of 1 (high). tms test mode select input this serial test mode input controls jtag mode selection. on-chip pull-up ensures a default value of 1 (high). the tms signal is sampled on the rising edge of the tck signal. tdi data in input (oci enabled) serial test data input. on-chip pull-up ensures a default value of 1 (high). this pin is input-only when the oci is enabled. the input data is sampled on the rising edge of the tck signal. i/o (oci disabled) when the oci is disabled, this pin functions as the zda (zdi data) i/o pin. tdo data out output the output data changes on the falling edge of the tck signal. trigout trigger output output generates an active high trigger pulse when valid oci trigger events occur. output is tristate when no data is being driven out.
ps013012-1004 preliminary on-chip instrumentation ez80l92 mcu product specification 186 oci information requests for additional information regarding on-chip instrumentation, or to order oci debug tools, please contact: first silicon solutions, inc. 5440 sw w estgate drive, suite 240 portland, or 97221 phone: (503) 292-6730 fax: (503) 292-5840 www .fs2.com
ps013012-1004 preliminary ez80 ? cpu instruction set ez80l92 mcu product specification 187 ez80 ? cpu instruction set t ables 108 through 1 17 indicate the ez80 ? cpu instructions available for use with the ez80l92 . the instructions are grouped by class. more detailed information is available in the ez80 ? cpu user manual. t able 108. arithmetic instructions mnemonic instruction adc add with carry add add without carry cp compare with accumulator daa decimal adjust accumulator dec decrement inc increment mlt multiply neg negate accumulator sbc subtract with carry sub subtract without carry t able 109. bit manipulation instructions mnemonic instruction bit bit test res reset bit set set bit t able 1 10. block t ransfer and compare instructions mnemonic instruction cpd (cpdr) compare and decrement (with repeat) cpi (cpir) compare and increment (with repeat) ldd (lddr) load and decrement (with repeat) ldi (ldir) load and increment (with repeat)
ps013012-1004 preliminary ez80 ? cpu instruction set ez80l92 mcu product specification 188 t able 1 1 1. exchange instructions mnemonic instruction ex exchange registers exx exchange cpu multibyte register banks t able 1 12. input/output instructions mnemonic instruction in input from i/o in0 input from i/o on page 0 ind (indr) input from i/o and decrement (with repeat) indrx input from i/o and decrement memory address with stationary i/o address ind2 (ind2r) input from i/o and decrement (with repeat) indm (indmr) input from i/o and decrement (with repeat) ini (inir) input from i/o and increment (with repeat) inirx input from i/o and increment memory address with stationary i/o address ini2 (ini2r) input from i/o and increment (with repeat) inim (inimr) input from i/o and increment (with repeat) otdm (otdmr) output to i/o and decrement (with repeat) otdrx output to i/o and decrement memory address with stationary i/o address otim (otimr) output to i/o and increment (with repeat) otirx output to i/o and increment memory address with stationary i/o address out output to i/o out0 output to i/o on page 0 outd (otdr) output to i/o and decrement (with repeat) outd2 (otd2r) output to i/o and decrement (with repeat) outi (otir) output to i/o and increment (with repeat) outi2 (oti2r) output to i/o and increment (with repeat) tstio test i/o
ps013012-1004 preliminary ez80 ? cpu instruction set ez80l92 mcu product specification 189 t able 1 13. load instructions mnemonic instruction ld load lea load effective address pea push effective address pop pop push push t able 1 14. logical instructions mnemonic instruction and logical and cpl complement accumulator or logical or tst test accumulator xor logical exclusive or t able 1 15. processor control instructions mnemonic instruction ccf complement carry flag di disable interrupts ei enable interrupts halt halt im interrupt mode nop no operation rsmix reset mixed-memory mode flag scf set carry flag slp sleep stmix set mixed-memory mode flag
ps013012-1004 preliminary ez80 ? cpu instruction set ez80l92 mcu product specification 190 t able 1 16. program control instructions mnemonic instruction call call subroutine call cc conditional call subroutine djnz decrement and jump if nonzero jp jump jp cc conditional jump jr jump relative jr cc conditional jump relative ret return ret cc conditional return reti return from interrupt retn return from nonmaskable interrupt rst restart t able 1 17. rotate and shift instructions mnemonic instruction rl rotate left rla rotate leftCaccumulator rlc rotate left circular rlca rotate left circularCaccumulator rld rotate left decimal rr rotate right rra rotate rightCaccumulator rrc rotate right circular rrca rotate right circularCaccumulator rrd rotate right decimal sla shift left arithmetic sra shift right arithmetic srl shift right logical
ps013012-1004 preliminary op-code map ez80l92 mcu product specification 191 op-code map t ables 1 18 through 124 indicate the hex values for each of the ez80 ? instructions. t able 1 18. op code mapfir st op code lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 nop ld bc, mmn ld (bc),a inc bc inc b dec b ld b,n rlca ex af ,af add hl,bc ld a,(bc) dec bc inc c dec c ld c,n rrca 1 djnz d ld de, mmn ld (de),a inc de inc d dec d ld d,n rla jr d add hl,de ld a,(de) dec de inc e dec e ld e,n rra 2 jr nz,d ld hl, mmn ld (mmn), hl inc hl inc h dec h ld h,n daa jr z,d add hl,hl ld hl, (mmn) dec hl inc l dec l ld l,n cpl 3 jr nc,d ld sp , mmn ld (mmn), a inc sp inc (hl) dec (hl) ld (hl),n scf jr cf ,d add hl,sp ld a, (mmn) dec sp inc a dec a ld a,n ccf 4 .sis suf fix ld b,c ld b,d ld b,e ld b,h ld b,l ld b,(hl) ld b,a ld c,b .lis suf fix ld c,d ld c,e ld c,h ld c,l ld c,(hl) ld c,a 5 ld d,b ld d,c .sil suf fix ld d,e ld d,h ld d,l ld d,(hl) ld d,a ld e,b ld e,c ld e,d .lil suf fix ld e,h ld e,l ld e,(hl) ld e,a 6 ld h,b ld h,c ld h,d ld h,e ld h,h ld h,l ld h,(hl) ld h,a ld l,b ld l,c ld l,d ld l,e ld l,h ld l,l ld l,(hl) ld l,a 7 ld (hl),b ld (hl),c ld (hl),d ld (hl),e ld (hl),h ld (hl),l hal t ld (hl),a ld a,b ld a,c ld a,d ld a,e ld a,h ld a,l ld a,(hl) ld a,a 8 add a,b add a,c add a,d add a,e add a,h add a,l add a,(hl) add a,a adc a,b adc a,c adc a,d adc a,e adc a,h adc a,l adc a,(hl) adc a,a 9 sub a,b sub a,c sub a,d sub a,e sub a,h sub a,l sub a,(hl) sub a,a sbc a,b sbc a,c sbc a,d sbc a,e sbc a,h sbc a,l sbc a,(hl) sbc a,a a and a,b and a,c and a,d and a,e and a,h and a,l and a,(hl) and a,a xor a,b xor a,c xor a,d xor a,e xor a,h xor a,l xor a,(hl) xor a,a b or a,b or a,c or a,d or a,e or a,h or a,l or a,(hl) or a,a cp a,b cp a,c cp a,d cp a,e cp a,h cp a,l cp a,(hl) cp a,a c ret nz pop bc jp nz, mmn jp mmn call nz, mmn push bc add a,n rst 00h ret z ret jp z, mmn t able 1 19 call z, mmn call mmn adc a,n rst 08h d ret nc pop de jp nc, mmn out (n),a call nc, mmn push de sub a,n rst 10h ret cf exx jp cf , mmn in a,(n) call cf , mmn t able 120 sbc a,n rst 18h e ret po pop hl jp po, mmn ex (sp),hl call po, mmn push hl and a,n rst 20h ret pe jp (hl) jp pe, mmn ex de,hl call pe, mmn t able 121 xor a,n rst 28h f ret p pop af jp p , mmn di call p , mmn push af or a,n rst 30h ret m ld sp ,hl jp m, mmn ei call m, mmn t able 122 cp a,n rst 38h notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. and 4 a lower op code nibble mnemonic second operand upper op code nibble first operand a,h legend
ps013012-1004 preliminary op-code map ez80l92 mcu product specification 192 t able 1 19. op code mapsecond op code after 0cbh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 rlc b rlc c rlc d rlc e rlc h rlc l rlc (hl) rlc a rrc b rrc c rrc d rrc e rrc h rrc l rrc (hl) rrc a 1 rl b rl c rl d rl e rl h rl l rl (hl) rl a rr b rr c rr d rr e rr h rr l rr (hl) rr a 2 sla b sla c sla d sla e sla h sla l sla (hl) sla a sra b sra c sra d sra e sra h sra l sra (hl) sra a 3 srl b srl c srl d srl e srl h srl l srl (hl) srl a 4 bit 0,b bit 0,c bit 0,d bit 0,e bit 0,h bit 0,l bit 0,(hl) bit 0,a bit 1,b bit 1,c bit 1,d bit 1,e bit 1,h bit 1,l bit 1,(hl) bit 1,a 5 bit 2,b bit 2,c bit 2,d bit 2,e bit 2,h bit 2,l bit 2,(hl) bit 2,a bit 3,b bit 3,c bit 3,d bit 3,e bit 3,h bit 3,l bit 3,(hl) bit 3,a 6 bit 4,b bit 4,c bit 4,d bit 4,e bit 4,h bit 4,l bit 4,(hl) bit 4,a bit 5,b bit 5,c bit 5,d bit 5,e bit 5,h bit 5,l bit 5,(hl) bit 5,a 7 bit 6,b bit 6,c bit 6,d bit 6,e bit 6,h bit 6,l bit 6,(hl) bit 6,a bit 7,b bit 7,c bit 7,d bit 7,e bit 7,h bit 7,l bit 7,(hl) bit 7,a 8 res 0,b res 0,c res 0,d res 0,e res 0,h res 0,l res 0,(hl) res 0,a res 1,b res 1,c res 1,d res 1,e res 1,h res 1,l res 1,(hl) res 1,a 9 res 2,b res 2,c res 2,d res 2,e res 2,h res 2,l res 2,(hl) res 2,a res 3,b res 3,c res 3,d res 3,e res 3,h res 3,l res 3,(hl) res 3,a a res 4,b res 4,c res 4,d res 4,e res 4,h res 4,l res 4,(hl) res 4,a res 5,b res 5,c res 5,d res 5,e res 5,h res 5,l res 5,(hl) res 5,a b res 6,b res 6,c res 6,d res 6,e res 6,h res 6,l res 6,(hl) res 6,a res 7,b res 7,c res 7,d res 7,e res 7,h res 7,l res 7,(hl) res 7,a c set 0,b set 0,c set 0,d set 0,e set 0,h set 0,l set 0,(hl) set 0,a set 1,b set 1,c set 1,d set 1,e set 1,h set 1,l set 1,(hl) set 1,a d set 2,b set 2,c set 2,d set 2,e set 2,h set 2,l set 2,(hl) set 2,a set 3,b set 3,c set 3,d set 3,e set 3,h set 3,l set 3,(hl) set 3,a e set 4,b set 4,c set 4,d set 4,e set 4,h set 4,l set 4,(hl) set 4,a set 5,b set 5,c set 5,d set 5,e set 5,h set 5,l set 5,(hl) set 5,a f set 6,b set 6,c set 6,d set 6,e set 6,h set 6,l set 6,(hl) set 6,a set 7,b set 7,c set 7,d set 7,e set 7,h set 7,l set 7,(hl) set 7,a notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. res 4 a lower nibble of 2nd op code mnemonic second operand upper op code first operand 4,h of second nibble legend
ps013012-1004 preliminary op-code map ez80l92 mcu product specification 193 t able 120. op code mapsecond op code after 0ddh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 ld bc, (ix+d) add ix,bc ld (ix+d), bc 1 ld de, (ix+d) add ix,de ld (ix+d), de 2 ld ix, mmn ld (mmn), ix inc ix inc ixh dec ixh ld ixh,n ld hl, (ix+d) add ix,ix ld ix, (mmn) dec ix inc ixl dec ixl ld ixl,n ld (ix+d), hl 3 ld iy , (ix+d) inc (ix+d) dec (ix+d) ld (ix +d),n ld ix, (ix+d) add ix,sp ld (ix+d), iy ld (ix+d), ix 4 ld b,ixh ld b,ixl ld b, (ix+d) ld c,ixh ld c,ixl ld c, (ix+d) 5 ld d,ixh ld d,ixl ld d, (ix+d) ld e,ixh ld e,ixl ld e, (ix+d) 6 ld ixh,b ld ixh,c ld ixh,d ld ixh,e ld ixh,ixh ld ixh,ixl ld h, (ix+d) ld ixh,a ld ixl,b ld ixl,c ld ixl,d ld ixl,e ld ixl,ixh ld ixl,ixl ld l, (ix+d) ld ixl,a 7 ld (ix+d),b ld (ix+d),c ld (ix+d),d ld (ix+d),e ld (ix+d),h ld (ix+d),l ld (ix+d),a ld a,ixh ld a,ixl ld a, (ix+d) 8 add a,ixh add a,ixl add a, (ix+d) adc a,ixh adc a,ixl adc a, (ix+d) 9 sub a,ixh sub a,ixl sub a, (ix+d) sbc a,ixh sbc a,ixl sbc a, (ix+d) a and a,ixh and a,ixl and a, (ix+d) xor a,ixh xor a,ixl xor a, (ix+d) b or a,ixh or a,ixl or a, (ix+d) cp a,ixh cp a,ixl cp a, (ix+d) c t able 123 d e pop ix ex (sp),ix push ix jp (ix) f ld sp ,ix notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. ld 9 f mnemonic second operand first operand sp,ix lower nibble of 2nd op code upper op code of second nibble legend
ps013012-1004 preliminary op-code map ez80l92 mcu product specification 194 t able 121. op code mapsecond op code after 0edh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 in0 b,(n) out0 (n),b lea bc, ix+d lea bc, iy+d tst a,b ld bc, (hl) in0 c,(n) out0 (n),c tst a,c ld (hl), bc 1 in0 d,(n) out0 (n),d lea de, ix+d lea de, iy+d tst a,d ld de, (hl) in0 e,(n) out0 (n),e tst a,e ld(hl), de 2 in0 h,(n) out0 (n),h lea hl ,ix+d lea hl ,iy+d tst a,h ld hl, (hl) in0 l,(n) out0 (n),l tst a,l ld (hl), hl 3 ld iy , (hl) lea ix ,ix+d lea iy ,iy+d tst a,(hl) ld ix, (hl) in0 a,(n) out0 (n),a tst a,a ld (hl),iy ld (hl), ix 4 in b,(bc) out (bc),b sbc hl,bc ld (mmn), bc neg retn im 0 ld i,a in c,(c) out (c),c adc hl,bc ld bc, (mmn) ml t bc reti ld r,a 5 in d,(bc) out (bc),d sbc hl,de ld (mmn), de lea ix, iy+d lea iy , ix+d im 1 ld a,i in e,(c) out (c),e adc hl,de ld de, (mmn) ml t de im 2 ld a,r 6 ibn h,(c) out (bc),h sbc hl,hl ld (mmn), hl tst a,n pea ix+d pea iy+d rrd in l,(c) out (c),l adc hl,hl ld hl, (mmn) ml t hl ld mb,a ld a,mb rld 7 sbc hl,sp ld (mmn), sp tstio n slp in a,(c) out (c),a adc hl,sp ld sp , (mmn) ml t sp stmix rsmix 8 inim otim ini2 indm otdm ind2 9 inimr otimr ini2r indmr otdmr ind2r a ldi cpi ini outi outi2 ldd cpd ind outd outd2 b ldir cpir inir otir oti2r lddr cpdr indr otdr otd2r c inirx otirx indrx otdrx d e f notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. sbc 2 4 mnemonic second operand first operand hl,bc lower nibble of 2nd op code upper op code of second nibble legend
ps013012-1004 preliminary op-code map ez80l92 mcu product specification 195 t able 122. op code mapsecond op code after 0fdh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 ld bc, (iy+d) add iy ,bc ld (iy +d),bc 1 ld de, (iy+d) add iy ,de ld (iy +d),de 2 ld iy ,mmn ld (mmn),i y inc iy inc iyh dec iyh ld iyh,n ld hl, (iy+d) add iy ,iy ld iy , (mmn) dec iy inc iyl dec iyl ld iyl,n ld (iy +d),hl 3 ld ix, (iy+d) inc (iy+d) dec (iy+d) ld (iy +d),n ld iy , (iy+d) add iy ,sp ld (iy +d),ix ld (iy +d),iy 4 ld b,iyh ld b,iyl ld b, (iy+d) ld c,iyh ld c,iyl ld c, (iy+d) 5 ld d,iyh ld d,iyl ld d, (iy+d) ld e,iyh ld e,iyl ld e, (iy+d) 6 ld iyh,b ld iyh,c ld iyh,d ld iyh,e ld iyh,iyh ld iyh,iyl ld h, (iy+d) ld iyh,a ld iyl,b ld iyl,c ld iyl,d ld iyl,e ld iyl,iyh ld iyl,iyl ld l, (iy+d) ld iyl,a 7 ld (iy +d),b ld (iy +d),c ld (iy +d),d ld (iy +d),e ld (iy +d),h ld (iy +d),l ld (iy +d),a ld a,iyh ld a,iyl ld a, (iy+d) 8 add a,iyh add a,iyl add a, (iy+d) adc a,iyh adc a,iyl adc a, (iy+d) 9 sub a,iyh sub a,iyl sub a, (iy+d) sbc a,iyh sbc a,iyl sbc a, (iy+d) a and a,iyh and a,iyl and a, (iy+d) xor a,iyh xor a,iyl xor a, (iy+d) b or a,iyh or a,iyl or a, (iy+d) cp a,iyh cp a,iyl cp a, (iy+d) c t able 124 d e pop iy ex (sp),iy push iy jp (iy) f ld sp ,iy notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. ld 9 f mnemonic second operand first operand sp,iy lower nibble of 2nd op code upper op code of second nibble legend
ps013012-1004 preliminary op-code map ez80l92 mcu product specification 196 t able 123. op code mapfourth byte after 0ddh, 0cbh, and dd lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 rlc (ix+d) rrc (ix+d) 1 rl (ix+d) rr (ix+d) 2 sla (ix+d) sra (ix+d) 3 srl (ix+d) 4 bit 0, (ix+d) bit 1, (ix+d) 5 bit 2, (ix+d) bit 3, (ix+d) 6 bit 4, (ix+d) bit 5, (ix+d) 7 bit 6, (ix+d) bit 7, (ix+d) 8 res 0, (ix+d) res 1, (ix+d) 9 res 2, (ix+d) res 3, (ix+d) a res 4, (ix+d) res 5, (ix+d) b res 6, (ix+d) res 7, (ix+d) c set 0, (ix+d) set 1, (ix+d) d set 2, (ix+d) set 3, (ix+d) e set 4, (ix+d) set 5, (ix+d) f set 6, (ix+d) set 7, (ix+d) notes: d = 8-bit twos-complement displacement. bit 6 4 lower nibble of 4th byte mnemonic second operand upper byte first operand 0,(ix+d) of fourth nibble legend
ps013012-1004 preliminary op-code map ez80l92 mcu product specification 197 t able 124. op code mapfourth byte after 0fdh, 0cbh, and dd* lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 rlc (iy+d) rrc (iy+d) 1 rl (iy+d) rr (iy+d) 2 sla (iy+d) sra (iy+d) 3 srl (iy+d) 4 bit 0, (iy+d) bit 1, (iy+d) 5 bit 2, (iy+d) bit 3, (iy+d) 6 bit 4, (iy+d) bit 5, (iy+d) 7 bit 6, (iy+d) bit 7, (iy+d) 8 res 0, (iy+d) res 1, (iy+d) 9 res 2, (iy+d) res 3, (iy+d) a res 4, (iy+d) res 5, (iy+d) b res 6, (iy+d) res 7, (iy+d) c set 0, (iy+d) set 1, (iy+d) d set 2, (iy+d) set 3, (iy+d) e set 4, (iy+d) set 5, (iy+d) f set 6, (iy+d) set 7, (iy+d) notes: d = 8-bit twos-complement displacement. bit 6 4 lower nibble of 4th byte mnemonic second operand upper byte first operand 0,(iy+d) of fourth nibble legend
ps013012-1004 preliminary on-chip oscillators ez80l92 mcu product specification 198 on-chip oscillators the ez80l92 mcu f eatu res two on-chip oscillators for use with an external crystal. the primary oscillator generates the system clock for the internal cpu and the majority of the on-chip peripherals. alternatively , the x in input pin can also accept a cmos-level clock input signal. if an external clock generator is used, the x out pin should be left uncon - nected. the secondary oscillator can drive a 32 khz crystal to generate the time-base for the real-t ime clock. 20 mhz primary crystal oscillator operation figure 44 illustrates a recommended configuration for connection with an external 20mhz, fundamental-mode, parallel-resonant crystal. recommended crystal specifica - tions are provided in t able 125 . resistor r 1 limits total power dissipation by the crystal. printed circuit board layout should add no more than 4pf of stray capacitance to either the x in or x out pins. if oscillation does not occur , reduce the values of capacitors c 1 and c 2 to decrease loading. figure 44. recommended crystal oscillator configuration (20mhz operation) x c = 22 pf in x out 2 r = 220 ? 1 r = 100 k? 2 c = 22 pf 2 20 mhz crystal (fundamental mode) on-chip oscillator
ps013012-1004 preliminary on-chip oscillators ez80l92 mcu product specification 199 32 khz real-time clock crystal oscillator operation figure 45 illustrates a recommended configuration for connecting the real-t ime clock oscillator with an external 32 khz, fundamental-mode, parallel-resonant crystal. the rec - ommended crystal specifications are provided in t able 126 . a printed circuit board layout should add no more than 4 pf of stray capacitance to either the r tc_x in or r tc_x out pins. if oscillation does not occur , reduce the values of capacitors c 1 and c 2 to decrease loading. an on-chip mos resistor sets the crystal drive current limit. this configuration does not require an external bias resistor across the crystal. an on-chip mos resistor provides the biasing. t able 125. recommended crystal oscillator specifications (20 mhz operation) parameter v alue units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s ) 25 ? maximum load capacitance (c l ) 20 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum figure 45. recommended crystal oscillator configuration (32khz operation) r tc_x c = 18 pf in r tc_x out 2 r = 220 ? 1 c = 18 pf 2 32 khz crystal (fundamental mode) on-chip oscillator
ps013012-1004 preliminary on-chip oscillators ez80l92 mcu product specification 200 t able 126. recommended crystal oscillator specifications (32 khz operation) parameter v alue units comments frequency 32 khz 32768 hz resonance parallel mode fundamental series resistance (r s ) 40 k? maximum load capacitance (c l ) 12.5 pf maximum shunt capacitance (c 0 ) 3 pf maximum drive level 1 w maximum
ps013012-1004 preliminary electrical characteristics ez80l92 mcu product specification 201 electrical characteristics absolute maximum ratings stresses greater than those listed in t able 127 may cause permanent damage to the device. these ratings are stress ratings only . operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability . for improved reliability , unused inputs should be tied to one of the supply voltages ( v dd or v ss ). t able 127. absolute maximum ratings parameter min max units notes ambient temperature under bias (oc) C40 +105 c 1 storage temperature (oc) C65 +150 c voltage on any pin with respect to v ss C0.3 +6.0 v 2 voltage on v dd pin with respect to v ss C0.3 +6.0 v total power dissipation 520 mw maximum current out of v ss 145 ma maximum current into v dd 145 ma maximum current on input and/or inactive output pin C15 +15 a maximum output current from active output pin C8 +8 ma notes: 1. operating temperature is specified in dc characteristics. 2. this voltage applies to all pins except where noted otherwise.
ps013012-1004 preliminary dc characteristics ez80l92 mcu product specification 202 dc characteristics t able 128 lists the dc characteristics of the ez80l92 . figures 46 and 47 plot supply cur - rent values against cpu frequency and wait states. all data is preliminary and subject to change following completion of production characterization. t able 128. dc characteristics symbol parameter t a = 0oc to 70oc t a = C40oc to 105oc units conditions min max min max v dd supply voltage 3.0 3.6 3.0 3.6 v v il low level input voltage C0.3 0.8 C0.3 0.8 v v ih high level input voltage 0.7 x v dd 5.5 0.7 x v dd 5.5 v v ol low level output voltage 0.4 0.4 v v dd = 3.0 v; i ol = 1 ma v oh high level output voltage 2.4 2.4 v v dd = 3.0 v; i oh = C1 ma i il input leakage current C10 +10 C10 +10 a v dd = 3.6v; v in = v dd or v ss 1 i tl tristate leakage current C10 +10 C10 +10 a v dd = 3.6 v i dd power dissipation (normal operation) 100 100 ma f = 20 mhz 145 145 ma f = 50 mhz power dissipation (halt mode) 10 10 ma f = 20 mhz 20 20 ma f = 50 mhz power dissipation (sleep mode) 10 25 a internal clocks stopped rtc_v dd rtc supply voltage 3.0 3.6 3.0 3.6 v i rtc rtc supply current 2.5 typical 10 2.5 typical 10 a supply current into rtc_ v dd note: 1 this condition excludes all pins with on-chip pull-ups when driven low. note:
ps013012-1004 preliminary dc characteristics ez80l92 mcu product specification 203 figure 46. i cc vs. frequency (t ypical @ 3.3 v , 25oc) figure 47. i cc vs. w ait ( t y pical @ 3.3 v , 25oc) 0 20 40 60 80 100 120 140 01020304 05060 0 wait 2 wait 7 wait 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 012345678 wait states cu rre nt ( ma ) 10 mhz 20 mhz 30 mhz 40 mhz 50 mhz l og. (10 mhz) l og. (50 mhz)
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 204 ac characteristics the section provides information about the ac characteristics and timing of the ez80l92 . all ac timing information assumes a standard load of 50 pf on all outputs. see t able 129 . all data is preliminary and subject to change following completion of production characterization. t able 129. ac characteristics symbol parameter t a = 0oc to 70oc t a = C40oc to 105oc units conditions min max min max t xin system clock cycle time 20 20 ns v dd = 3.0 C 3.6v t xinh system clock high time 10 10 ns v dd = 3.0 C 3.6v; t clk = 50ns t xinl system clock low time 10 10 ns v dd = 3.0 C 3.6v; t clk = 50ns t xinr system clock rise time 3 3 ns v dd = 3.0 C 3.6v; t clk = 50ns t xinf system clock fall time 3 3 ns v dd = 3.0 C 3.6v; t clk = 50ns note:
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 205 external memory read timing figure 48 and t able 130 diagram the timing for external reads. figure 48. external memory read t iming t able 130. external read t iming parameter description 20 mhz (ns) 50 mhz (ns) min. max. min. max. t 1 clock rise to addr valid delay 10.2 10.2 t 2 clock rise to addr hold time 2.4 2.4 t 3 input data valid to clock rise setup time 1.0 1.0 t 4 data hold time from clock rise 2.4 2.4 t 5 clock rise to csx assertion delay 3.2 10.3 3.2 10.3 t 6 clock rise to csx deassertion delay 2.9 9.7 2.9 9.7 t 7 clock rise to mreq assertion delay 2.8 9.6 2.8 9.6 x addr[23:0] data[7:0] (input) csx mreq rd in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 206 external memory write timing figure 49 and t able 50 diagram the timing for external w rites. t 8 clock rise to mreq deassertion delay 2.6 6.9 2.6 6.9 t 9 clock rise to rd assertion delay 3.0 9.8 3.0 9.8 t 10 clock rise to rd deassertion delay 2.6 7.1 2.6 7.1 figure 49. external memory w rite t iming t able 130. external read t iming (continued) parameter description 20 mhz (ns) 50 mhz (ns) min. max. min. max. x addr[23:0] data[7:0] (output) csx mreq wr in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 207 figure 50. external w rite t iming parameter description 20 mhz (ns) 50 mhz (ns) min. max. min. max. t 1 clock rise to addr valid delay 10.2 10.2 t 2 clock rise to addr hold time 2.4 2.4 t 3 clock fall to output data valid delay 6 6 t 4 data hold time from clock rise 2.4 2.4 t 5 clock rise to csx assertion delay 3.2 10.3 3.2 10.3 t 6 clock rise to csx deassertion delay 2.9 9.7 2.9 9.7 t 7 clock rise to mreq assertion delay 2.8 9.6 2.8 9.6 t 8 clock rise to mreq deassertion delay 2.6 6.9 2.6 6.9 t 9 clock fall to wr assertion delay 1.5 5.0 1.5 5.0 t 10 clock rise to wr deassertion delay* 1.4 3.6 1.4 3.6 note: *at the conclusion of a wr ite cycle, deassertion of wr always occurs before any change to addr, data, csx , or mreq . in certain applications, the deassertion of wr can be concurrent with addr, data, csx , or mreq when buffering is used off-chip.
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 208 external i/o read timing figure 51 and t able 131 diagram the timing for external i/o reads. figure 51. external i/o read t iming t able 131. external i/o read t iming parameter abbreviation 20 mhz (ns) 50 mhz (ns) min max min. max. t 1 clock rise to addr valid delay 6.9 6.9 t 2 clock rise to addr hold time 2.2 2.2 t 3 input data valid to clock rise setup time 0.4 0.4 t 4 clock rise to data hold time 1.3 1.3 t 5 clock rise to csx assertion delay 2.6 10.8 2.6 10.8 t 6 clock rise to csx deassertion delay 2.4 8.8 2.4 8.8 t 7 clock rise to iorq assertion delay 2.6 7.0 2.6 7.0 t 8 clock rise to iorq deassertion delay 2.3 6.3 2.3 6.3 x addr[23:0] data[7:0] (input) csx iorq rd in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 209 external i/o write timing figure 52 and t able 132 diagram the timing for external i/o w rites. t 9 clock rise to rd assertion delay 2.7 7.0 2.7 7.0 t 10 clock rise to rd deassertion delay 2.4 6.3 2.4 6.3 figure 52. external i/o w rite t iming t able 131. external i/o read t iming (continued) parameter abbreviation 20 mhz (ns) 50 mhz (ns) min max min. max. x addr[23:0] data[7:0] (output) csx iorq wr in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 210 t able 132. external i/o w rite t iming parameter abbreviation 20 mhz (ns) 50 mhz (ns) min max min. max. t 1 clock rise to addr valid delay 7.7 7.7 t 2 clock rise to addr hold time 2.2 2.2 t 3 clock fall to output data valid delay 6 6 t 4 clock rise to data hold time 2.3 2.3 t 5 clock rise to csx assertion delay 2.6 10.8 2.6 10.8 t 6 clock rise to csx deassertion delay 2.4 8.8 2.4 8.8 t 7 clock rise to iorq assertion delay 2.6 7.0 2.6 7.0 t 8 clock rise to iorq deassertion delay 2.3 6.3 2.3 6.3 t 9 clock fall to wr assertion delay 1.8 4.5 1.8 4.5 t 10 clock rise to wr deassertion delay* 1.6 4.4 1.6 4.4 wr deassertion to addr hold time 0.4 0.4 wr deassertion to data hold time 0.5 0.5 wr deassertion to csx hold time 1.2 1.2 wr deassertion to iorq hold time 0.5 0.5 note: *at the conclusion of a write cycle, deassertion of wr always occurs before any change to addr, data, csx , or iorq . in certain applications, the deassertion of wr can be concurrent with addr, data, csx , or mreq when buffering is used off-chip.
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 211 wait state timing for read operations figure 53 illustrates the extension of the memory access signals using a single wait state for a read operation. this w ait state is generated by setting cs_w ait to 001 in the chip select control register . figure 53. w ait state t iming for read operations t clk w ait t csx_wait x addr[23:0] data[7:0] (input) csx mreq rd in instrd t
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 212 wait state timing for write operations figure 54 illustrates the extension of the memory access signals using a single wait state for a w rite operation. this w ait state is generated by setting cs_w ait to 001 in the chip select control register . figure 54. w ait state t iming for w rite operations t clk t clk x addr[23:0] data[7:0] (output) csx mreq wr in
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 213 general purpose i/o port input sample timing figure 55 illustrates timing of the gpio input sampling. the input value on a gpio port pin is sampled on the rising edge of the system clock. the port value is then available to the cpu on the second rising clock edge following the change of the port value. general purpose i/o port output timing figure 56 and t able 133 provide timing information for gpio port pins. figure 55. port input sample t iming figure 56. gpio port output t iming t clk system clock gpio pin input value gpio input data latch gpio data read on data bus port value changes to 0 0 latched into gpio data register gpio data register v alue 0 read by ez80 t clk extal port output t 1 t 2
ps013012-1004 preliminary ac characteristics ez80l92 mcu product specification 214 external bus acknowledge timing t able 134 provides information about the bus acknowledge timing. external system clock driver (phi) timing t able 135 provides timing information for the phi pin. the phi pin allows external peripherals to synchronize with the internal system clock driver on the ez80l92 . t able 133. gpio port output t iming parameter abbreviation 20 mhz (ns) 50 mhz (ns) min max min max t 1 clock rise to port output valid delay 9.3 9.3 t 2 clock rise to port output hold time 2.0 2.0 t able 134. bus acknowledge t iming parameter abbreviation 20 mhz (ns) 50 mhz (ns) min max min max t 1 clock rise to busack assertion delay 2.8 9.3 2.8 9.3 t 2 clock rise to busack deassertion delay 2.5 6.5 2.5 6.5 t able 135. phi system clock t iming parameter abbreviation 20 mhz (ns) 50 mhz (ns) min max min max t 1 clock rise to phi rise 1.6 4.6 1.6 4.6 t 2 clock fall to phi fall 1.8 4.3 1.8 4.3
ps013012-1004 preliminary ez80l92 mcu product specification 215 packaging figure 57 illustrates the 100-pin lqfp (low-profile quad flat pack) package for the ez80l92 devices. figure 57. 100-lead plastic low-profile quad flat package (lqfp)
ps013012-1004 preliminary ez80l92 mcu product specification 216 ordering information t able 136 provides a part number , a product specification index code, and a brief descrip - tion of each ez80l92 part. navigate your browser to zilog s website to order the ez80l92 mcu. or , contact your local zilog sales of ? ce to order these devices. zilog provides additional assistance on its customer service page, and is also here to help with technical support issues. for zilog s valuable softw are de v elopment tools and do wnloadable softw are , visit the zilog website . part number description zilog part numbers consist of a number of components, as indicated in the following examples: t able 136. ordering information part psi description ez80l92 ez80l92az020s c, ez80l92az020sg 100-pin lqfp, 20 mhz, standard temperature ez80l92 EZ80L92AZ020EC , ez80l92az020eg 100-pin lqfp, 20 mhz, extended temperature ez80l92 ez80l92az050sc , ez80l92az050sg 100-pin lqfp, 50 mhz, standard temperature ez80l92 ez80l92az050ec , ez80l92az050eg 100-pin lqfp, 50 mhz, extended temperature zilog base products ez80 zilog ez80 ? cpu l92 product number az package 050 speed s or e t emperature c or g environmental flow
ps013012-1004 preliminary ez80l92 mcu product specification 217 example: part number ez80l92az020sc is an ez80 ? cpu product in a lqfp package, operating with a 20-mhz external clock frequency over a 0oc to +70oc temperature range and built using the plastic standard environmental flow . precharacterization product the product represented by this document is newly introduced and zilog has not com - pleted the full characterization of the product. the document states what zilog knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery might be uncertain at times, due to start-up yield issues. zilog, inc. 532 race street san jose, ca 95126 t elephone (408) 558-8500 f ax 408 558-8300 internet: www .zilog.com package az = lqfp (also called the vqfp) speed 050 = 50 mhz standard temperature s = 0oc to +70oc extended temperature e = C40oc to +105oc environmental flow c = plastic standard; g = lead-free
ps013012-1004 preliminary document information ez80l92 mcu product specification 218 document information document number description the document control number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table: change log ps product specification 0130 unique document number 1 2 revision number 090 4 month and year published rev date purpose by 01 01/02 original issue d. wilson, r. beebe 02 06/02 memory timing revisions j. eversmann, r. beebe 03 06/02 memory timing revisions j. eversmann, r. beebe 04 10/02 modifications to characteristics data j. eversmann, r. beebe 05 11/02 modifications to characteristics data j. eversmann, r. beebe 06 01/03 minor modifications to content r. beebe 07 02/03 minor modifications to content r. johnson, r. beebe 08 06/03 modifications to characteristics data c. bender 09 08/03 clarification to tables 24 and 25 e. aquino, r. beebe 10 09/03 minor modifications r. beebe 11 02/04 revisions to brg divisor, uart text r. beebe 12 09/04 revisions to timer control, timing diagrams r. beebe
ez80l92 mcu product specification ps013012-1004 preliminary index 219 index numerics 100-pin lqfp package 4 , 20 20 mhz primary crystal oscillator operation 198 32 khz real-time clock crystal oscillator operation 199 a absolute maximum ratings 20 1 a c characteristics 204 ack see acknowledge acknowledge 140, 144C 148, 150, 155C 156 addr0 5 , 20 addr1 5 , 2 0 a ddr2 5 , 20 addr3 5, 20 addr4 5, 20 addr5 5, 20 addr6 6, 21 addr7 6, 21 addr8 6, 21 addr9 6, 21 addr10 6, 21 addr11 7, 21 addr12 7, 21 addr13 7, 21 addr14 7, 21 addr15 7, 21 addr16 8, 21 addr17 8, 21 addr18 8, 21 addr19 8, 21 addr20 8 , 21 addr21 8 , 21 addr22 9 , 21 addr23 9 , 2 1 a ddress bus 5C 9, 46 , 50 , 52 C 5 7 , 60 , 63 C 6 4 , 67 C 6 8 , 90 , 166 , 176 , 182 2 4-bit 25 addressing 150 arbitration 142 architectural overview 1 asynchronous serial data 13 , 15 b baud rate generator 104 , 108 f unctional description 131 block diagram 2 brg control registers 109 bus arbitration overview 138 bus mode controller 53 bus acknowledge 11, 22, 52, 166, 176, 182, 214 bus request 11, 22, 52, 166, 176, 182 d uring zdi debug mode 166 busack see bus acknowledge busreq see bus request byte format 140 c change log 218 characteristics, electrical absolute maximum ratings 201 chip select registers 66 chip select x bus mode control register 70 chip select x control register 69 chip select x lower bound register 66 chip select x upper bound register 68 chip select/wait state generator block 5 , 6 , 7 , 8 , 9 chip selects and wait states 48 chip selects during bus request/bus acknowledge cycles 52 clear to send 14 , 16 , 117, 120 delta status change of 120 clock peripheral power-down registers 36 clock phase bit 128, 130, 134 clock polarity bit 129- 130, 134 c lock synchronization 141 clocking overview 138
ez80l92 mcu product specification ps013012-1004 preliminary index 220 continuous mo de 78 cpha see clock phase cpol see clock polarity bit c s0 9 , 21 , 48 C 5 1 cs1 9 , 21 , 48 C 5 1 cs2 9 , 21 , 48 , 50 C 5 1 cs3 9 , 21 , 48 , 50 C 5 1 cts see clear to send cts0 14 , 124 cts1 16 customer feedback form 226 customer information 226 cycle termination signal 63C 64 d d ata bus 9C 10, 52 C 5 3 , 55 C 5 7 , 60, 64 , 70 , 90 , 166 , 176 , 182 data carrier detect 14 , 17 , 117, 120 delta status change of 120 data set ready 14 , 16 , 117, 120 delta status change of 120 data terminal ready 14 , 16 , 117, 120 d ata transfer procedure with spi configured as a slave 132 data transfer procedure with spi configured as the master 132 data transfer, spi 135 data validity 139 data0 9 , 21 data1 9 , 22 data2 10 , 22 data3 10 , 22 data4 10 , 22 data5 10 , 22 data6 10 , 22 data7 10 , 22 dc characteristics 202 dcd see data carrier detect dcd0 14 , 124 dcd1 17 dcts see clear to send, delta status change of ddcd see data carrier detect, delta status change of ddsr see data set ready, delta status change of document information 218 document number description 218 dsr see data set ready dsr0 14 , 124 dsr1 16 dtack see cycle termination signal dt rsee data terminal ready dtr0 14 , 124 dtr1 16 e edge-triggered interrupts 42 ei see interrupt enable e lectrical characteristics 201 enabling and disabling the wdt 73 endecsee infrared data association encoder/ decoder event counter 79 external bus acknowledge timing 214 external i/o read timing 208 external i/o write timing 209 external memory read timing 205 external memory write timing 206 external system clock driver (phi) timing 214 ez80 cpu 34 C 3 6 , 51 C 5 2 , 56 C 5 7 , 63 C 6 4 , 122 , 168 , 184 ez80 cpu core 32 ez80 cpu instruction set 187 ez80 product id low and high byte registers 179 ez80 product id revision register 18 0 f f ast mode 138 , 158 features 1 e z80 cpu core 32 full-duplex transmission 130 functional description, infrared encoder/decoder 122
ez80l92 mcu product specification ps013012-1004 preliminary index 221 g g eneral-purpose input/output 39 control registers 43 interrupts 42 operation 39 overview 39 port input sample timing 213 port output timing 213 g nd see ground gpiosee general-purpose input/output ground 2 h h alt instruction 11, 35, 172, 180, 189 h alt mode 1 , 35C 36 halt, op-code map 191 i i/o chip select operation 50 i/o space 5 , 6 , 7 , 8 , 9 , 10 , 48 , 50 i 2 c see inter-integrated circuit iefsee interrupt enable flag i ef1 46 C 4 7 , 181 ief2 46 C 4 7 im 0, op code map 194 im 1, op code map 194 im 2, op code map 194 infrared data association 122 encoder/decoder 13, 37, 122, 125 receive data 13 specifications 122 standard baud rates 122 transceiver 125 transmit data 13 r egister 125 s ignal pins 124 input/output request 10C 11, 22, 51, 53C 54, 56C 57, 60 assertion delay 208, 210 deassertion delay 208, 210 hold time 210 instrd see instruction read instruction read 11, 22 i nstruction store 4 0 registers 17 7 i ntel bus mode 55 m ultiplexed address and data bus 6 0 s eparate address and data buses 5 6 inter-integrated circuit clock control register 157 control register 152 data register 152 general characteristics 138 registers 150 serial i/o interface 138 slave address register 150 software reset register 158 status register 155 i nternal pull-up 40 interrupt controller 45 in terrupt en able 11 , 89, 106, 152 op code map 191 i nterrupt enable flag 47, 18 1 i nterrupt input 13 C 1 6 , 18 C 2 0 , 125 introduction to on-chip instrumentation 184 introduction, zilog debug interface 159 iorq see input/output request i rda see infrared data association 1 2 2 irq_en 81 , 131 , 134 irq_en bit 79 j jitter, infrared encoder/decoder 124 jtag test mode 12 l level-triggered interrupts 42 loopback testing, infrared encoder/decoder 125 low-power modes 35 m maskable interrupts 45
ez80l92 mcu product specification ps013012-1004 preliminary index 222 master mode 129 , 138 , 148C 149, 1 52 , 154C 1 5 8 s tart bit 152 s top bit 152 s pi 130 master receive mode 1 38 , 14 6 m aster transmit mode 138 , 143 master_en bit 131 master-in, slave-out 19, 128C 130 master-out, slave-in 128 memory and i/o chip selects 48 memory chip select example 49 memory chip select operation 48 memory chip select priority 49 memory request 10C 11, 22, 48, 53C 54, 56C 57, 60 memory space 48 , 50 miso see master-in, slave-out m ode fault error flag 128 , 131, 135 m odem status signal 14 , 16 modf see mode fault error flag mosi see master-out, slave-in 1 28 C 1 30 motorola bus mode 62 motorola-compatible 53 mreq see memory request multimaster conflict 131 , 135 n nack see not acknowledge new and improved instructions, ez80 cpu core 32 nmi 11 , 22 , 32 , 36 , 47 , 72 , 73 , 74 nonmaskable interrupts 47 not acknowledge 140, 144C 148, 153, 156 o ocisee on-chip instrumentation o n-chip instrumentation 184 activation 184 information requests 186 interface 185 on-chip oscillators 198 op code maps 19 1 o pen-drain output 40, 1 38 open-source output 13 C 1 6 , 18 C 2 0 operating modes 143 operation of the ez80l92 mcu d uring zdi breakp oints 165 ordering information 216 overview, low-power modes 35 p packaging 215 part number description 216 pb0 18 , 23 , 79 pb1 18 , 23 , 79 pb2 18 , 24 pb3 18 , 24 pb4 19 , 24 , 41 , 80 pb5 19 , 24 , 80 pb6 19 , 24 pb7 20 , 24 , 39 pc0 15 , 23 pc1 15 , 23 pc2 16 , 23 pc3 16 , 23 pc4 16 , 23 pc5 16 , 23 pc6 17 , 23 pc7 17 , 23 , 41 pd0 13 , 125 pd1 13 , 23 , 125 pd2 13 , 23 , 125 pd3 14 , 23 pd4 14 , 23 pd5 14 , 23 pd6 14 , 23 pd7 15 , 23 , 125 pin characteristics 20 pin description 4 pop, op code map 191 , 193 , 195 port x alternate register 1 44 port x alternate register 2 44 port x data direction registers 44 port x data registers 43 power connections 2 precharacterization product 217
ez80l92 mcu product specification ps013012-1004 preliminary index 223 problem description or suggestion 226 product information 226 programmable reload timer operation 77 programmable reload timer registers 81 programmable reload timers 76 programmable reload timers overview 76 pull-up resistor, external 40 , 138 push, op code map 191 , 193 , 195 r rd see read instruction read instruction 10C 11, 22, 48, 51, 53, 56C 57, 60 assertion delay 209 deassertion delay 209 r eading the current count value 79 real-time clock 88 a larm 89 a larm control register 102 a larm day-of-the-week register 101 a larm hours register 100 a larm minutes register 99 a larm seconds register 98 b attery backup 89 c entury register 97 c ontrol register 102 d ay-of-the-month register 94 d ay-of-the-week register 93 h ours register 92 m inutes register 91 m onth register 95 o scillator and source selection 89 o verview 88 r ecommended operation 89 r egisters 90 s econds register 90 y ear register 96 receive, infrared encoder/decoder 123 recommended usage of the baud rate generator 109 register map 25 request to send 13 , 16 , 117, 120, 124 reset 10 C 1 1, 22, 34C 3 6, 39C 40, 48, 72 C 7 4, 89 C 9 0, 102, 109, 125, 132, 170, 172, 184 C 1 8 5 o r nmi generation 73 reset states 49 resetting the i 2 c r egisters 150 return information 226 ri see ring indicator ri0 15 , 124 ri1 17 , 41 ring indicator 15 , 17 , 106, 117, 120 rts see request to send rts0 13 rts1 16 rxd0 13 rxd1 15 s schmitt trigger 11 sck see system clock, spi s cl see system clock , i 2 c scl line 141 C 1 43 sda see serial data, i 2 c serial bus, spi 136 , 137 serial clock 129 , 138 i 2 c 2 0 s pi 18, 12 8 se rial da ta 128 , 138 i 2 c 20, 24, 138C 140, 142, 149 serial peripheral interface 1, 37, 45, 127C 128, 130 baud rate generator 131 baud rate generator register 28 baud rate generator registerslow byte and high byte 132 block 28 control register 28, 134 data rate 131 flags 130C131, 135C 137 functional description 130 interrupt service routine 45 master device 19C 20, 132 master mode 130 mode 18 receive buffer register 28, 137 registers 132 serial bus 136
ez80l92 mcu product specification ps013012-1004 preliminary index 224 serial clock 18 signals 128 slave device 19, 20 slave mode 130 status register 28, 131, 135 transmit shift register 28, 131C 132, 136 s etting timer duration 77 shift left arithmetic 145, 147, 151, 190 op code map 192, 196C 197 shift right arithmetic 190 op code map 192, 196 s ingle pass mo de 77 sla see shift left arithmetic s lave mode 138, 149C 1 52, 15 6 s pi 130 slave receive 138 , 149 slave select 18, 128C 130, 132, 134 slave transmit 138 , 148 sleep mo de 35 spi see serial peripheral interface s pif see serial peripheral interface flags s ra see shift right arithmetic s s see slave select sta see master mode start bit standard mode 138 start and stop co nditions 13 9 s upply voltage 1 , 40 , 138 , 201 C 202 switching between bus modes 6 6 system clock , i 2 c 20, 24, 138C 140, 157 system clock, spi 18, 128C 129 idle state 129 pin 130, 134 receive edge 129 signal 130 transmit edge 129 system clock cycles 11 , 51 , 53 C 5 4 , 57 , 61 , 64 , 73 , 184 system clock oscillator input 17 system clock oscillator output 1 7 t teri 120 test mode 185 time-out period selection 73 timer control register 81 timer data registerhigh byte 83 timer data registerlow byte 82 timer input source select register 86 timer input source selection 79 timer output 80 timer reload registerhigh byte 85 transferring data 140 transmit, infrared encoder/decoder 123 txd0 13 txd1 15 u uartsee universal asynchronous receiver/ transmitter u niversal asynchronous receiver/transmitter 104 baud rate generator register low and high bytes 109 fifo control register 114 functional description 104 interrupt enable register 112 interrupt identification register 113 interrupts 106 line control register 115 line status register 118 modem control 106 modem control register 117 modem status interrupt 107 modem status register 120 receive buffer register 111 receiver 105 receiver interrupts 106 recommended usage 107 registers 110 scratch pad register 121 transmit holding register 110 transmitter 105 transmitter interrupt 106
ez80l92 mcu product specification ps013012-1004 preliminary index 225 v v cc 2 w wait 1 , 11 , 22 , 57 , 60 , 63 C 6 4 i nput signal 51 p in, external 53 C 5 4 wait state 54 , 61 , 211 C 2 12 t iming for read operations 211 t iming for write operations 212 wait states 46 , 51, 57 , 60 , 69 , 16 6 w atch-dog timer 72 c ontrol register 74 o peration 73 o verview 72 r egisters 74 r eset register 75 wcol see write collision wdtsee watch-dog timer w r see write instruction write collision 130C 131, 135 s pi 135 write instruction 10C 11, 22, 48, 51, 54, 57, 60, 210 z z 80 bus mode 53 zcl see zilog debug interface clock zda see zilog debug interface data zdisee zilog debug interface z di_bus_stat 166 , 168 , 182 zdi_busack_en 166 , 182 z di-supported protocol 160 zilog debug interface 159 address match registers 168 block read 165 block write 164 break control register 169 bus control register 176 bus status register 182 clock 161, 163, 170 clock and data conventions 161 data 161, 170, 185 master control register 172 read memory register 183 read operations 164 read register low, high, and upper 181 read/write control register 174 read-only registers 168 register addressing 162 register definitions 168 single-byte read 164 single-byte write 163 start condition 161 status register 180 write data registers 173 write memory register 178 write operations 163 write-only registers 167
ps013012-1004 preliminary customer feedback form ez80l92 mcu product specification 226 customer feedback form the ez80l92 product specification if you experience any problems while operating this product, or if you note any inaccuracies while reading this product specification , please copy and complete this form, then mail or fax it to zilog (see return information , below). w e also welcome your suggestions! customer information product information return information zilog inc. system t est/customer support 532 race street san jose, ca 95126 phone: (408) 558-8495 email: tools@zilog.com problem description or suggestion provide a complete description of the problem or your suggestion. if you are reporting a specific problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary . _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ name country company phone address fax city/state/zip email serial # or board fab #/rev. # software version document number host computer description/type

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